boards: arm: mimxrt1024_evk: enable flexcan1
Enable FlexCAN1 on the NXP i.MX RT1024 Evaluation Kit. Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
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@ -83,6 +83,8 @@ features:
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| ENET | on-chip | ethernet |
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| ENET | on-chip | ethernet |
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+-----------+------------+-------------------------------------+
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+-----------+------------+-------------------------------------+
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| CAN | on-chip | can |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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The default configuration can be found in the defconfig file:
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``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
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``boards/arm/mimxrt1024_evk/mimxrt1024_evk_defconfig``
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@ -129,6 +131,10 @@ The MIMXRT1024 SoC has five pairs of pinmux/gpio controllers.
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_EMC_40 | ENET_MDIO | Ethernet |
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| GPIO_EMC_40 | ENET_MDIO | Ethernet |
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+---------------+-----------------+---------------------------+
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B1_00 | FLEXCAN1_TX | CAN TX |
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+---------------+-----------------+---------------------------+
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| GPIO_SD_B1_01 | FLEXCAN1_RX | CAN RX |
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+---------------+-----------------+---------------------------+
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System Clock
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System Clock
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============
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============
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@ -26,6 +26,7 @@
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zephyr,dtcm = &dtcm;
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zephyr,dtcm = &dtcm;
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zephyr,console = &lpuart1;
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zephyr,console = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,shell-uart = &lpuart1;
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zephyr,can-primary = &flexcan1;
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};
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};
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sdram0: memory@80000000 {
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sdram0: memory@80000000 {
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@ -91,3 +92,8 @@
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status = "okay";
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status = "okay";
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current-speed = <115200>;
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current-speed = <115200>;
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};
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};
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&flexcan1 {
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status = "okay";
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bus-speed = <125000>;
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};
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@ -16,3 +16,4 @@ ram: 32768
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flash: 4096
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flash: 4096
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supported:
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supported:
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- netif:eth
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- netif:eth
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- can
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@ -88,6 +88,15 @@ static int mimxrt1024_evk_init(const struct device *dev)
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GPIO_WritePinOutput(GPIO1, 4, 0);
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GPIO_WritePinOutput(GPIO1, 4, 0);
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#endif
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcan1), okay) && CONFIG_CAN
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/* FlexCAN1 TX, RX */
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, 1);
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IOMUXC_SetPinMux(IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, 1);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_00_FLEXCAN1_TX, 0x10B0u);
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IOMUXC_SetPinConfig(IOMUXC_GPIO_SD_B1_01_FLEXCAN1_RX, 0x10B0u);
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#endif
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return 0;
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return 0;
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}
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}
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