diff --git a/CODEOWNERS b/CODEOWNERS index 26205f82411..544d8cf1f39 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -210,6 +210,7 @@ /dts/arm/nordic/ @ioannisg @carlescufi /dts/arm/nxp/ @MaureenHelm /dts/arm/microchip/ @franciscomunoz @albertofloyd @scottwcpg +/dts/arm/silabs/efm32gg11b* @oanerer /dts/riscv/microsemi-miv.dtsi @galak /dts/riscv/rv32m1* @MaureenHelm /dts/riscv/riscv32-fe310.dtsi @nategraff-sifive diff --git a/boards/arm/efm32gg_stk3701a/CMakeLists.txt b/boards/arm/efm32gg_stk3701a/CMakeLists.txt new file mode 100644 index 00000000000..5c1455add76 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/CMakeLists.txt @@ -0,0 +1,9 @@ +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if(CONFIG_UART_GECKO) + zephyr_library() + zephyr_library_sources(board.c) + zephyr_library_include_directories(${PROJECT_SOURCE_DIR}/drivers) +endif() diff --git a/boards/arm/efm32gg_stk3701a/Kconfig b/boards/arm/efm32gg_stk3701a/Kconfig new file mode 100644 index 00000000000..d708b33429a --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/Kconfig @@ -0,0 +1,16 @@ +# EFM32GG STK3701A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_STK3701A + +config BOARD_INIT_PRIORITY + int + default KERNEL_INIT_PRIORITY_DEFAULT + depends on GPIO + help + Board initialization priority. This must be bigger than + GPIO_GECKO_COMMON_INIT_PRIORITY. + +endif # BOARD_EFM32GG_STK3701A diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.board b/boards/arm/efm32gg_stk3701a/Kconfig.board new file mode 100644 index 00000000000..77b8cdfaa00 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/Kconfig.board @@ -0,0 +1,10 @@ +# EFM32GG STK3701A board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_EFM32GG_STK3701A + bool "SiLabs EFM32GG-STK3701A (Giant Gecko 11)" + depends on SOC_SERIES_EFM32GG11B + select SOC_PART_NUMBER_EFM32GG11B820F2048GL192 + select HAS_DTS_I2C diff --git a/boards/arm/efm32gg_stk3701a/Kconfig.defconfig b/boards/arm/efm32gg_stk3701a/Kconfig.defconfig new file mode 100644 index 00000000000..c76083a2037 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/Kconfig.defconfig @@ -0,0 +1,66 @@ +# EFM32GG STK3701A default board configuration +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_EFM32GG_STK3701A + +config BOARD + string + default "efm32gg_stk3701a" + +config CMU_HFXO_FREQ + default 50000000 + +config CMU_LFXO_FREQ + default 32768 + +if GPIO_GECKO + +config GPIO_GECKO_PORTA + default y + +config GPIO_GECKO_PORTB + default y + +config GPIO_GECKO_PORTC + default y + +config GPIO_GECKO_PORTD + default y + +config GPIO_GECKO_PORTE + default y + +config GPIO_GECKO_PORTF + default y + +config GPIO_GECKO_PORTG + default y + +config GPIO_GECKO_PORTH + default y + +config GPIO_GECKO_PORTI + default y + +endif # GPIO_GECKO + +if COUNTER + +config COUNTER_GECKO_RTCC + default y + +endif # COUNTER + +if NETWORKING + +config NET_L2_ETHERNET + default y + +config ETH_GECKO + default y if NET_L2_ETHERNET + +endif # NETWORKING + +endif # BOARD_EFM32GG_STK3701A diff --git a/boards/arm/efm32gg_stk3701a/board.c b/boards/arm/efm32gg_stk3701a/board.c new file mode 100644 index 00000000000..2bdeeacf102 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/board.c @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include "board.h" +#include +#include +#include "em_cmu.h" + +static int efm32gg_stk3701a_init(struct device *dev) +{ + struct device *cur_dev; + + ARG_UNUSED(dev); + + /* Enable the board controller to be able to use the serial port */ + cur_dev = device_get_binding(BC_ENABLE_GPIO_NAME); + if (!cur_dev) { + printk("Board controller gpio port was not found!\n"); + return -ENODEV; + } + + gpio_pin_configure(cur_dev, BC_ENABLE_GPIO_PIN, GPIO_DIR_OUT); + gpio_pin_write(cur_dev, BC_ENABLE_GPIO_PIN, 1); + +#ifdef CONFIG_ETH_GECKO + /* Enable the ethernet PHY power */ + cur_dev = device_get_binding(ETH_PWR_ENABLE_GPIO_NAME); + if (!cur_dev) { + printk("Ethernet PHY power gpio port was not found!\n"); + return -ENODEV; + } + + gpio_pin_configure(cur_dev, ETH_PWR_ENABLE_GPIO_PIN, GPIO_DIR_OUT); + gpio_pin_write(cur_dev, ETH_PWR_ENABLE_GPIO_PIN, 1); + + /* Configure ethernet reference clock */ + cur_dev = device_get_binding(ETH_REF_CLK_GPIO_NAME); + if (!cur_dev) { + printk("Ethernet reference clock gpio port was not found!\n"); + return -ENODEV; + } + + gpio_pin_configure(cur_dev, ETH_REF_CLK_GPIO_PIN, GPIO_DIR_OUT); + gpio_pin_write(cur_dev, ETH_REF_CLK_GPIO_PIN, 0); + + /* enable CMU_CLK2 as RMII reference clock */ + CMU->CTRL |= CMU_CTRL_CLKOUTSEL2_HFXO; + CMU->ROUTELOC0 = (CMU->ROUTELOC0 & ~_CMU_ROUTELOC0_CLKOUT2LOC_MASK) | + (ETH_REF_CLK_LOCATION << _CMU_ROUTELOC0_CLKOUT2LOC_SHIFT); + CMU->ROUTEPEN |= CMU_ROUTEPEN_CLKOUT2PEN; + + /* Release the ethernet PHY reset */ + cur_dev = device_get_binding(ETH_RESET_GPIO_NAME); + if (!cur_dev) { + printk("Ethernet PHY reset gpio port was not found!\n"); + return -ENODEV; + } + + gpio_pin_configure(cur_dev, ETH_RESET_GPIO_PIN, GPIO_DIR_OUT); + gpio_pin_write(cur_dev, ETH_RESET_GPIO_PIN, 1); +#endif /* CONFIG_ETH_GECKO */ + + return 0; +} + +/* needs to be done after GPIO driver init */ +SYS_INIT(efm32gg_stk3701a_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY); diff --git a/boards/arm/efm32gg_stk3701a/board.cmake b/boards/arm/efm32gg_stk3701a/board.cmake new file mode 100644 index 00000000000..a3ced2516fa --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/board.cmake @@ -0,0 +1,6 @@ +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(jlink "--device=EFM32GG11B820F2048") +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/arm/efm32gg_stk3701a/board.h b/boards/arm/efm32gg_stk3701a/board.h new file mode 100644 index 00000000000..e0c8207b1d9 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/board.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef __INC_BOARD_H +#define __INC_BOARD_H + +/* This pin is used to enable the serial port using the board controller */ +#define BC_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTE_NAME +#define BC_ENABLE_GPIO_PIN 1 + +/* Ethernet specific pins */ +#ifdef CONFIG_ETH_GECKO +#define ETH_PWR_ENABLE_GPIO_NAME DT_GPIO_GECKO_PORTI_NAME +#define ETH_PWR_ENABLE_GPIO_PIN 10 + +#define ETH_RESET_GPIO_NAME DT_GPIO_GECKO_PORTH_NAME +#define ETH_RESET_GPIO_PIN 7 + +#define ETH_REF_CLK_GPIO_NAME DT_GPIO_GECKO_PORTD_NAME +#define ETH_REF_CLK_GPIO_PIN DT_INST_0_SILABS_GECKO_ETHERNET_LOCATION_RMII_REFCLK_2 +#define ETH_REF_CLK_LOCATION DT_INST_0_SILABS_GECKO_ETHERNET_LOCATION_RMII_REFCLK_0 + +#endif /* CONFIG_ETH_GECKO */ + +#endif /* __INC_BOARD_H */ diff --git a/boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg b/boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg new file mode 100644 index 00000000000..38a341d79b9 Binary files /dev/null and b/boards/arm/efm32gg_stk3701a/doc/efm32gg_stk3701a.jpg differ diff --git a/boards/arm/efm32gg_stk3701a/doc/index.rst b/boards/arm/efm32gg_stk3701a/doc/index.rst new file mode 100644 index 00000000000..9ae36169909 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/doc/index.rst @@ -0,0 +1,200 @@ +.. _efm32gg_stk3701a: + +EFM32 Giant Gecko GG11 Starter Kit +################################## + +Overview +******** + +The EFM32 Giant Gecko Starter Kit EFM32GG-STK3701A contains an MCU from the +EFM32GG Series 1 family built on an ARM® Cortex®-M4F processor with excellent +low power capabilities. + +.. figure:: ./efm32gg_stk3701a.jpg + :width: 375px + :align: center + :alt: EFM32GG-SLSTK3701A + + EFM32GG-SLSTK3701A (image courtesy of Silicon Labs) + +Hardware +******** + +- Advanced Energy Monitoring provides real-time information about the energy + consumption of an application or prototype design. +- Ultra low power 128x128 pixel color Memory-LCD +- 2 user buttons, 2 LEDs and a touch slider +- Relative humidity, magnetic Hall Effect and inductive-capacitive metal sensor +- USB interface for Host/Device/OTG +- 32 Mb Quad-SPI Flash memory +- SD card slot +- RJ-45 Ethernet jack +- 2 digital microphones +- On-board Segger J-Link USB debugger + +For more information about the EFM32GG11 SoC and EFM32GG-STK3701A board: + +- `EFM32GG Series 1 Website`_ +- `EFM32GG11 Datasheet`_ +- `EFM32GG11 Reference Manual`_ +- `EFM32GG-STK3701A Website`_ +- `EFM32GG-STK3701A User Guide`_ +- `EFM32GG-STK3701A Schematics`_ + +Supported Features +================== + +The efm32gg_stk3701a board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| COUNTER | on-chip | rtcc | ++-----------+------------+-------------------------------------+ +| ETHERNET | on-chip | ethernet | ++-----------+------------+-------------------------------------+ +| FLASH | on-chip | flash memory | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| I2C | on-chip | i2c port-polling | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + ``boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig`` + +Other hardware features are currently not supported by the port. + +Connections and IOs +=================== + +The EFM32GG11 SoC has nine GPIO controllers (PORTA to PORTI), all of which are +currently enabled for the EFM32GG-STK3701A board. + +In the following table, the column **Name** contains pin names. For example, PE1 +means pin number 1 on PORTE, as used in the board's datasheets and manuals. + ++-------+-------------+-------------------------------------+ +| Name | Function | Usage | ++=======+=============+=====================================+ +| PH10 | GPIO | LED0 red | ++-------+-------------+-------------------------------------+ +| PH11 | GPIO | LED0 green | ++-------+-------------+-------------------------------------+ +| PH12 | GPIO | LED0 blue | ++-------+-------------+-------------------------------------+ +| PH13 | GPIO | LED1 red | ++-------+-------------+-------------------------------------+ +| PH14 | GPIO | LED1 green | ++-------+-------------+-------------------------------------+ +| PH15 | GPIO | LED1 blue | ++-------+-------------+-------------------------------------+ +| PC8 | GPIO | Push Button PB0 | ++-------+-------------+-------------------------------------+ +| PC9 | GPIO | Push Button PB1 | ++-------+-------------+-------------------------------------+ +| PE1 | GPIO | Board Controller Enable | +| | | EFM_BC_EN | ++-------+-------------+-------------------------------------+ +| PH4 | UART_TX | UART TX Console VCOM_TX US0_TX #4 | ++-------+-------------+-------------------------------------+ +| PH5 | UART_RX | UART RX Console VCOM_RX US0_RX #4 | ++-------+-------------+-------------------------------------+ +| PI4 | I2C_SDA | SENSOR_I2C_SDA I2C2_SDA #7 | ++-------+-------------+-------------------------------------+ +| PI5 | I2C_SCL | SENSOR_I2C_SCL I2C2_SCL #7 | ++-------+-------------+-------------------------------------+ + + +System Clock +============ + +The EFM32GG11 SoC is configured to use the 50 MHz external oscillator on the +board. + +Serial Port +=========== + +The EFM32GG11 SoC has six USARTs, two UARTs and two Low Energy UARTs (LEUART). +USART4 is connected to the board controller and is used for the console. + +Programming and Debugging +************************* + +.. note:: + Before using the kit the first time, you should update the J-Link firmware + from `J-Link-Downloads`_ + +Flashing +======== + +The EFM32GG-STK3701A includes an `J-Link`_ serial and debug adaptor built into the +board. The adaptor provides: + +- A USB connection to the host computer, which exposes a mass storage device and a + USB serial port. +- A serial flash device, which implements the USB flash disk file storage. +- A physical UART connection which is relayed over interface USB serial port. + +Flashing an application to EFM32GG-STK3701A +------------------------------------------- + +The sample application :ref:`hello_world` is used for this example. +Build the Zephyr kernel and application: + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: efm32gg_stk3701a + :goals: build + +Connect the EFM32GG-STK3701A to your host computer using the USB port and you +should see a USB connection which exposes a mass storage device(STK3701A) and +a USB Serial Port. Copy the generated zephyr.bin to the STK3701A drive. + +Open a serial terminal (minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Reset the board and you'll see the following message on the corresponding serial port +terminal session: + +.. code-block:: console + + Hello World! efm32gg_stk3701a + + +.. _EFM32GG-STK3701A Website: + https://www.silabs.com/products/development-tools/mcu/32-bit/efm32-giant-gecko-gg11-starter-kit + +.. _EFM32GG-STK3701A User Guide: + https://www.silabs.com/documents/public/user-guides/ug287-stk3701.pdf + +.. _EFM32GG-STK3701A Schematics: + https://www.silabs.com/documents/public/schematic-files/BRD2204A-B00-schematic.pdf + +.. _EFM32GG Series 1 Website: + https://www.silabs.com/products/mcu/32-bit/efm32-giant-gecko-s1 + +.. _EFM32GG11 Datasheet: + https://www.silabs.com/documents/public/data-sheets/efm32gg11-datasheet.pdf + +.. _EFM32GG11 Reference Manual: + https://www.silabs.com/documents/public/reference-manuals/efm32gg11-rm.pdf + +.. _J-Link: + https://www.segger.com/jlink-debug-probes.html + +.. _J-Link-Downloads: + https://www.segger.com/downloads/jlink diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts new file mode 100644 index 00000000000..693160f7142 --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.dts @@ -0,0 +1,141 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include + +/ { + model = "Silicon Labs EFM32GG STK3701A board"; + compatible = "silabs,efm32gg_stk3701a", "silabs,efm32gg11b"; + + chosen { + zephyr,console = &usart4; + zephyr,shell-uart = &usart4; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + }; + + /* These aliases are provided for compatibility with samples */ + aliases { + led0 = &led0; + led1 = &led1; + sw0 = &button0; + sw1 = &button1; + }; + + leds { + compatible = "gpio-leds"; + led0: led_0 { + gpios = <&gpioh 10 0>; + label = "LED 0"; + }; + led1: led_1 { + gpios = <&gpioh 13 0>; + label = "LED 1"; + }; + }; + + buttons { + compatible = "gpio-keys"; + button0: button_0 { + /* gpio flags need validation */ + gpios = <&gpioc 8 GPIO_INT_ACTIVE_LOW>; + label = "User Push Button 0"; + }; + button1: button_1 { + /* gpio flags need validation */ + gpios = <&gpioc 9 GPIO_INT_ACTIVE_LOW>; + label = "User Push Button 1"; + }; + }; +}; + +&usart0 { + current-speed = <115200>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&usart4 { + current-speed = <115200>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&leuart0 { + current-speed = <9600>; + location-rx = ; + location-tx = ; + status = "okay"; +}; + +&i2c0 { + location-sda = ; + location-scl = ; + status = "okay"; +}; + +&i2c1 { + location-sda = ; + location-scl = ; + status = "okay"; +}; + +&rtcc0 { + prescaler = <1>; + status = "okay"; +}; + +&gpio { + location-swo = <0>; + status = "okay"; +}; + +ð0 { + /* local-mac-address = <>;*/ + + /* PHY address = 0 */ + phy-address = <0>; + + /* PHY management pins */ + location-mdio = ; + location-phy_mdc = ; + location-phy_mdio = ; + + /* RMII interface pins */ + location-rmii = ; + location-rmii_refclk = ; + location-rmii_crs_dv = ; + location-rmii_txd0 = ; + location-rmii_txd1 = ; + location-rmii_tx_en = ; + location-rmii_rxd0 = ; + location-rmii_rxd1 = ; + location-rmii_rx_er = ; + + status = "okay"; +}; + +&flash0 { + /* + * For more information, see: + * http://docs.zephyrproject.org/latest/guides/dts/index.html#flash-partitions + */ + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + /* Set 6Kb of storage at the end of the 2048Kb of flash */ + storage_partition: partition@1fe800 { + label = "storage"; + reg = <0x001fe800 0x00001800>; + }; + }; +}; diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml new file mode 100644 index 00000000000..2f59628591e --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a.yaml @@ -0,0 +1,18 @@ +identifier: efm32gg_stk3701a +name: EFM32GG-STK3701A +type: mcu +arch: arm +ram: 512 +flash: 2048 +toolchain: + - zephyr + - gccarmemb + - xtools +supported: + - i2c + - gpio + - netif:eth + - nvs +testing: + ignore_tags: + - bluetooth diff --git a/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig new file mode 100644 index 00000000000..6bf7e5973bb --- /dev/null +++ b/boards/arm/efm32gg_stk3701a/efm32gg_stk3701a_defconfig @@ -0,0 +1,14 @@ +# Copyright (c) 2019 Interay Solutions B.V. +# Copyright (c) 2019 Oane Kingma +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_ARM=y +CONFIG_SOC_SERIES_EFM32GG11B=y +CONFIG_BOARD_EFM32GG_STK3701A=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_CORTEX_M_SYSTICK=y +CONFIG_GPIO=y +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=50000000 +CONFIG_CMU_HFCLK_HFXO=y diff --git a/dts/arm/silabs/efm32gg11b.dtsi b/dts/arm/silabs/efm32gg11b.dtsi new file mode 100644 index 00000000000..49edd2a163f --- /dev/null +++ b/dts/arm/silabs/efm32gg11b.dtsi @@ -0,0 +1,276 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "gpio_gecko.h" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-m4f"; + reg = <0>; + }; + }; + + sram0: memory@20000000 { + device_type = "memory"; + compatible = "mmio-sram"; + }; + + soc { + flash-controller@40000000 { + compatible = "silabs,gecko-flash-controller"; + label = "FLASH_CTRL"; + reg = <0x40000000 0x110>; + interrupts = <33 0>; + + #address-cells = <1>; + #size-cells = <1>; + + flash0: flash@0 { + compatible = "soc-nv-flash"; + label = "FLASH_0"; + write-block-size = <4>; + erase-block-size = <2048>; + }; + }; + + rtcc0: rtcc@40062000 { /* RTCC0 */ + compatible = "silabs,gecko-rtcc"; + reg = <0x40062000 0x184>; + interrupts = <31 0>; + clock-frequency = <32768>; + prescaler = <1>; + status = "disabled"; + label = "RTCC_0"; + }; + + uart0: uart@40014000 { /* UART0 */ + compatible = "silabs,gecko-uart"; + reg = <0x40014000 0x400>; + interrupts = <21 0 22 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <0>; + status = "disabled"; + label = "UART_0"; + }; + + uart1: uart@40014400 { /* UART1 */ + compatible = "silabs,gecko-uart"; + reg = <0x40014400 0x400>; + interrupts = <23 0 24 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <1>; + status = "disabled"; + label = "UART_1"; + }; + + usart0: usart@40010000 { /* USART0 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010000 0x400>; + interrupts = <6 0 7 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <0>; + status = "disabled"; + label = "USART_0"; + }; + + usart1: usart@40010400 { /* USART1 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010400 0x400>; + interrupts = <17 0 18 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <1>; + status = "disabled"; + label = "USART_1"; + }; + + usart2: usart@40010800 { /* USART2 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010800 0x400>; + interrupts = <19 0 20 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <2>; + status = "disabled"; + label = "USART_2"; + }; + + usart3: usart@40010c00 { /* USART3 */ + compatible = "silabs,gecko-usart"; + reg = <0x40010c00 0x400>; + interrupts = <37 0 38 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <3>; + status = "disabled"; + label = "USART_3"; + }; + + usart4: usart@40011000 { /* USART4 */ + compatible = "silabs,gecko-usart"; + reg = <0x40011000 0x400>; + interrupts = <39 0 40 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <4>; + status = "disabled"; + label = "USART_4"; + }; + + usart5: usart@40011400 { /* USART5 */ + compatible = "silabs,gecko-usart"; + reg = <0x40011400 0x400>; + interrupts = <50 0 51 0>; + interrupt-names = "rx", "tx"; + peripheral-id = <5>; + status = "disabled"; + label = "USART_5"; + }; + + leuart0: leuart@4006a000 { /* LEUART0 */ + compatible = "silabs,gecko-leuart"; + reg = <0x4006a000 0x400>; + interrupts = <25 0>; + peripheral-id = <0>; + status = "disabled"; + label = "LEUART_0"; + }; + + leuart1: leuart@4006a400 { /* LEUART1 */ + compatible = "silabs,gecko-leuart"; + reg = <0x4006a400 0x400>; + interrupts = <26 0>; + peripheral-id = <1>; + status = "disabled"; + label = "LEUART_1"; + }; + + i2c0: i2c@40089000 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40089000 0x400>; + interrupts = <11 0>; + label = "I2C_0"; + status = "disabled"; + }; + + i2c1: i2c@40089400 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40089400 0x400>; + interrupts = <12 0>; + label = "I2C_1"; + status = "disabled"; + }; + + i2c2: i2c@40089800 { + compatible = "silabs,gecko-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x40089800 0x400>; + interrupts = <45 0>; + label = "I2C_2"; + status = "disabled"; + }; + + gpio: gpio@40088400 { + compatible = "silabs,efm32-gpio"; + reg = <0x40088400 0xc00>; + interrupts = <3 2 13 2>; + interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + label = "GPIO"; + + ranges; + #address-cells = <1>; + #size-cells = <1>; + + gpioa: gpio@40088000 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088000 0x30>; + label = "GPIO_A"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiob: gpio@40088030 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088030 0x30>; + label = "GPIO_B"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioc: gpio@40088060 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088060 0x30>; + label = "GPIO_C"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiod: gpio@40088090 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088090 0x30>; + label = "GPIO_D"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioe: gpio@400880c0 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x400880c0 0x30>; + label = "GPIO_E"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiof: gpio@400880f0 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x400880f0 0x30>; + label = "GPIO_F"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpiog: gpio@40088120 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088120 0x30>; + label = "GPIO_G"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioh: gpio@40088150 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088150 0x30>; + label = "GPIO_H"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioi: gpio@40088180 { + compatible = "silabs,efm32-gpio-port"; + reg = <0x40088180 0x30>; + label = "GPIO_I"; + gpio-controller; + #gpio-cells = <2>; + }; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi b/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi new file mode 100644 index 00000000000..ab18fba465a --- /dev/null +++ b/dts/arm/silabs/efm32gg11b820f2048gl192.dtsi @@ -0,0 +1,35 @@ +/* + * Copyright (c) 2019 Interay Solutions B.V. + * Copyright (c) 2019 Oane Kingma + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +/ { + sram0: memory@20000000 { + reg = <0x20000000 DT_SIZE_K(256)>; + }; + + soc { + compatible = "silabs,efm32gg11b820f2048gl192", "silabs,efm32gg11b", + "silabs,efm32", "simple-bus"; + + flash-controller@40000000 { + flash0: flash@0 { + reg = <0 DT_SIZE_K(2048)>; + }; + }; + + eth0: eth@40024000 { /* ETH0 */ + compatible = "silabs,gecko-ethernet"; + reg = <0x40024000 0xC14>; + interrupts = <59 0>; + status = "disabled"; + label = "ETH_0"; + }; + }; + +};