From c5094b82f59c768eeaac63c8899ff014fabf2606 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?=C3=98yvind=20R=C3=B8nningstad?= Date: Thu, 20 Feb 2020 15:31:42 +0100 Subject: [PATCH] soc: arm: nrf53: defconfig: Add config for Erratum 19 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Erratum 19: SPU region size is 32 kB instead of 16 kB. The config should be used for alignment for data that must follow SPU region boundaries, and to enable runtime checks when configuring SPU regions. Signed-off-by: Øyvind Rønningstad --- .../nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA index 9901e2f2505..0808111d8c9 100644 --- a/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA +++ b/soc/arm/nordic_nrf/nrf53/Kconfig.defconfig.nrf5340_CPUAPP_QKAA @@ -11,4 +11,18 @@ config SOC config NUM_IRQS default 69 +config NRF5340_CPUAPP_ERRATUM19 + bool "Include workarounds for Erratum 19" + default y + depends on !TRUSTED_EXECUTION_NONSECURE + help + This anomaly applies to IC Rev. Engineering A, build codes QKAA-AB0. + This config MUST be enabled if there is a chance the code will be run + on nRF5340 Engineering A. Enabling this config is safe on other + nRF5340 variants, but might increase flash size. + The workaround involves adding run-time checks when using the SPU, + and aligning regions on 32 KiB instead of 16 KiB if they are to be + locked with the SPU. + More info: https://infocenter.nordicsemi.com/topic/errata_nRF5340_EngA/ERR/nRF5340/EngineeringA/latest/anomaly_340_19.html?cp=3_0_1_0_1_15 + endif # SOC_NRF5340_CPUAPP_QKAA