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drivers/clock_control: stm32_common: Add elementary PLL configuration step

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Introduce a set_up_pll configuration function and make PLL configuration
an elementary step of the whole system clock configuration.

To implement this new, function make use of the existing series specific
files which allows series specific configuration when required.

Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2022-03-23 15:34:16 +01:00 • committed by Carles Cufí
commit c4ff7d1e19
9 changed files with 255 additions and 207 deletions
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30
drivers/clock_control/clock_stm32l4_l5_wb_wl.c
View file

@ -27,19 +27,39 @@
#define pllr(v) z_pllr(v)
/**
* @brief fill in pll configuration structure
* @brief Set up pll configuration
*/
void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
int config_pll_sysclock(void)
{
pllinit->PLLM = pllm(STM32_PLL_M_DIVISOR);
pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
uint32_t pll_source, pll_m, pll_n, pll_r;
#ifdef PWR_CR5_R1MODE
/* set power boost mode for sys clock greater than 80MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
LL_PWR_EnableRange1BoostMode();
}
#endif /* PWR_CR5_R1MODE */
pll_n = STM32_PLL_N_MULTIPLIER;
pll_m = pllm(STM32_PLL_M_DIVISOR);
pll_r = pllr(STM32_PLL_R_DIVISOR);
/* Configure PLL source */
if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
pll_source = LL_RCC_PLLSOURCE_HSI;
} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
pll_source = LL_RCC_PLLSOURCE_HSE;
} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
pll_source = LL_RCC_PLLSOURCE_MSI;
} else {
return -ENOTSUP;
}
LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_m, pll_n, pll_r);
LL_RCC_PLL_EnableDomain_SYS();
return 0;
}
#endif /* STM32_SYSCLK_SRC_PLL */