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arch: arm64: add GIC ICC system register accessors

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-Add GIC system register defines.
-Add sysreg read write macros.

Signed-off-by: Sandeep Tripathy <sandeep.tripathy@broadcom.com>
This commit is contained in:
Sandeep Tripathy 2020-04-27 20:55:20 +05:30 • committed by Andrew Boie
commit c4e0b28bb5
1 changed files with 40 additions and 0 deletions
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40
include/arch/arm/aarch64/cpu.h
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@ -66,6 +66,46 @@
#define SPSR_EL3_h BIT(0)
#define SPSR_EL3_TO_EL1 (0x2 << 1)
/* System register interface to GICv3 */
#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
#define ICC_SGI1R S3_0_C12_C11_5
#define ICC_SRE_EL1 S3_0_C12_C12_5
#define ICC_SRE_EL2 S3_4_C12_C9_5
#define ICC_SRE_EL3 S3_6_C12_C12_5
#define ICC_CTLR_EL1 S3_0_C12_C12_4
#define ICC_CTLR_EL3 S3_6_C12_C12_4
#define ICC_PMR_EL1 S3_0_C4_C6_0
#define ICC_RPR_EL1 S3_0_C12_C11_3
#define ICC_IGRPEN1_EL3 S3_6_C12_C12_7
#define ICC_IGRPEN0_EL1 S3_0_C12_C12_6
#define ICC_HPPIR0_EL1 S3_0_C12_C8_2
#define ICC_HPPIR1_EL1 S3_0_C12_C12_2
#define ICC_IAR0_EL1 S3_0_C12_C8_0
#define ICC_IAR1_EL1 S3_0_C12_C12_0
#define ICC_EOIR0_EL1 S3_0_C12_C8_1
#define ICC_EOIR1_EL1 S3_0_C12_C12_1
#define ICC_SGI0R_EL1 S3_0_C12_C11_7
/* register constants */
#define ICC_SRE_ELx_SRE BIT(0)
#define ICC_SRE_ELx_DFB BIT(1)
#define ICC_SRE_ELx_DIB BIT(2)
#define ICC_SRE_EL3_EN BIT(3)
#ifndef _ASMLANGUAGE
/* Core sysreg macros */
#define read_sysreg(reg) ({ \
u64_t val; \
__asm__ volatile("mrs %0, " STRINGIFY(reg) : "=r" (val));\
val; \
})
#define write_sysreg(val, reg) ({ \
__asm__ volatile("msr " STRINGIFY(reg) ", %0" : : "r" (val));\
})
#endif /* !_ASMLANGUAGE */
#define __ISB() __asm__ volatile ("isb sy" : : : "memory")
#define __DMB() __asm__ volatile ("dmb sy" : : : "memory")