boards: arm: Add NXP i.MX8MQ EVK board support
Add board support for NXP i.MX8MQ EVK. More information about this board can be found in NXP website: https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK Signed-off-by: Kwon Tae-young <tykwon@m2i.co.kr>
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8
boards/arm/mimx8mq_evk/CMakeLists.txt
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boards/arm/mimx8mq_evk/CMakeLists.txt
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#
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_library()
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zephyr_library_sources(pinmux.c)
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9
boards/arm/mimx8mq_evk/Kconfig.board
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boards/arm/mimx8mq_evk/Kconfig.board
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# MIMX8MQ EVK board
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MIMX8MQ_EVK_CM4
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bool "NXP i.MX8MQ EVK"
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depends on SOC_SERIES_IMX8MQ_M4
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select SOC_PART_NUMBER_MIMX8MQ6DVAJZ
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boards/arm/mimx8mq_evk/Kconfig.defconfig
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boards/arm/mimx8mq_evk/Kconfig.defconfig
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# MIMX8MQ EVK board defconfig
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_MIMX8MQ_EVK_CM4
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config BOARD
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default "mimx8mq_evk_cm4"
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if !XIP
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config FLASH_SIZE
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default 0
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config FLASH_BASE_ADDRESS
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default 0
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endif
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endif # BOARD_MIMX8MQ_EVK_CM4
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boards/arm/mimx8mq_evk/board.cmake
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boards/arm/mimx8mq_evk/board.cmake
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#
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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board_set_debugger_ifnset(jlink)
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board_set_flasher_ifnset(jlink)
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board_runner_args(jlink "--device=MIMX8MQ6_M4")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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BIN
boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg
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BIN
boards/arm/mimx8mq_evk/doc/img/mimx8mq_evk.jpg
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184
boards/arm/mimx8mq_evk/doc/index.rst
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boards/arm/mimx8mq_evk/doc/index.rst
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.. _mimx8mq_evk:
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NXP MIMX8MQ EVK
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###############
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Overview
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********
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i.MX8MQ EVK board is based on NXP i.MX8MQ applications
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processor, composed of a quad Cortex®-A53 cluster and a single Cortex®-M4 core.
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Zephyr OS is ported to run on the Cortex®-M4 core.
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- Board features:
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- RAM: 3GB LPDDR4
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- Storage:
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- 16GB eMMC5.0
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- 32MB QSPI NOR
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- microSD Socket
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- Wireless:
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- WiFi: 2.4/5GHz IEEE 802.11 a/b/g/n/ac
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- Bluetooth: v4.1
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- USB:
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- OTG - 1x type C
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- HOST - 1x type A
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- Ethernet
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- PCI-E M.2
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- LEDs:
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- 1x Power status LED
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- 1x UART LED
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- Debug
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- JTAG 10-pin connector
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- MicroUSB for UART debug, two COM ports for A53 and M4
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.. image:: img/mimx8mq_evk.jpg
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:width: 720px
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:align: center
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:height: 405px
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:alt: MIMX8MQ EVK
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More information about the board can be found at the
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`NXP website`_.
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Supported Features
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==================
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The Zephyr mimx8mq_evk board configuration supports the following hardware
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features:
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+-----------+------------+-------------------------------------+
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| Interface | Controller | Driver/Component |
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+===========+============+=====================================+
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| NVIC | on-chip | nested vector interrupt controller |
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+-----------+------------+-------------------------------------+
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| SYSTICK | on-chip | systick |
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+-----------+------------+-------------------------------------+
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| CLOCK | on-chip | clock_control |
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+-----------+------------+-------------------------------------+
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| PINMUX | on-chip | pinmux |
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+-----------+------------+-------------------------------------+
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| UART | on-chip | serial port-polling; |
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| | | serial port-interrupt |
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+-----------+------------+-------------------------------------+
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The default configuration can be found in the defconfig file:
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:zephyr_file:`boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig`.
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Other hardware features are not currently supported by the port.
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Connections and IOs
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===================
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MIMX8MQ EVK board was tested with the following pinmux controller
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configuration.
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+---------------+-----------------+---------------------------+
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| Board Name | SoC Name | Usage |
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+===============+=================+===========================+
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| UART2 RXD | UART2_TXD | UART Console |
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+---------------+-----------------+---------------------------+
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| UART2 TXD | UART2_RXD | UART Console |
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+---------------+-----------------+---------------------------+
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System Clock
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============
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The M4 Core is configured to run at a 266 MHz clock speed.
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Serial Port
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===========
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The i.MX8MQ SoC has four UARTs. UART_2 is configured for the console and
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the remaining are not used/tested.
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Programming and Debugging
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*************************
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The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs
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to be started by the A53 core. The A53 core is responsible to load the M4 binary
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application into the RAM, put the M4 in reset, set the M4 Program Counter and
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Stack Pointer, and get the M4 out of reset. The A53 can perform these steps at
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bootloader level or after the Linux system has booted.
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The M4 can use up to 3 different RAMs. These are the memory mapping for A53 and M4:
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| Region | Cortex-A53 | Cortex-M4 (System Bus) | Cortex-M4 (Code Bus) | Size |
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+============+=========================+========================+=======================+======================+
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| OCRAM | 0x00900000-0x0091FFFF | 0x20200000-0x2021FFFF | 0x00900000-0x0091FFFF | 128KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| TCMU | 0x00800000-0x0081FFFF | 0x20000000-0x2001FFFF | | 128KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| TCML | 0x007E0000-0x007FFFFF | | 0x1FFE0000-0x1FFFFFFF | 128KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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| OCRAM_S | 0x00180000-0x00187FFF | 0x20180000-0x20187FFF | 0x00180000-0x00187FFF | 32KB |
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+------------+-------------------------+------------------------+-----------------------+----------------------+
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For more information about memory mapping see the
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`i.MX 8M Applications Processor Reference Manual`_ (section 2.1.2 and 2.1.3)
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At compilation time you have to choose which RAM will be used. This
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configuration is done in the file ``boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts``
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with "zephyr,flash" (when CONFIG_XIP=y) and "zephyr,sram" properties.
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The available configurations are:
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.. code-block:: none
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"zephyr,flash"
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- &tcml_code
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- &ocram_code
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- &ocram_s_code
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"zephyr,sram"
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- &tcmu_sys
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- &ocram_sys
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- &ocram_s_sys
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Load and run Zephyr on M4 from A53 using u-boot by copying the compiled
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``zephyr.bin`` to the first FAT partition of the SD card and plug the SD
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card into the board. Power it up and stop the u-boot execution at prompt.
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Load the M4 binary onto the desired memory and start its execution using:
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.. code-block:: console
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fatload mmc 0:1 0x40480000 zephyr.bin
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cp.b 0x40480000 0x7e0000 0x8000
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bootaux 0x7e0000
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Debugging
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=========
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MIMX8MQ EVK board can be debugged by connecting an external JLink
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JTAG debugger to the J401 debug connector and to the PC. Then
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the application can be debugged using the usual way.
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Here is an example for the :ref:`hello_world` application.
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: mimx8mq_evk_cm4
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:goals: debug
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Open a serial terminal, step through the application in your debugger, and you
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should see the following message in the terminal:
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.. code-block:: console
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***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 *****
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Hello World! mimx8mq_evk_cm4
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References
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==========
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.. _NXP website:
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https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK
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.. _i.MX 8M Applications Processor Reference Manual:
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https://www.nxp.com/webapp/Download?colCode=IMX8MDQLQRM
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.dts
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/*
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* Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nxp/nxp_imx8mq_m4.dtsi>
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/ {
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model = "NXP i.MX8MQ EVK board";
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compatible = "nxp,mimx8mq_evk";
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aliases {
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uart-2 = &uart2;
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};
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chosen {
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zephyr,flash = &tcml_code;
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zephyr,sram = &tcmu_sys;
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zephyr,console = &uart2;
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zephyr,shell-uart = &uart2;
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};
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};
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&uart2 {
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status = "okay";
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current-speed = <115200>;
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};
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4.yaml
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#
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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identifier: mimx8mq_evk_cm4
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name: NXP i.MX8MQ EVK CM4
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type: mcu
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arch: arm
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ram: 32
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flash: 32
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toolchain:
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- zephyr
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- gnuarmemb
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- xtools
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testing:
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ignore_tags:
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- net
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- bluetooth
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig
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boards/arm/mimx8mq_evk/mimx8mq_evk_cm4_defconfig
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#
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# Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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CONFIG_SOC_SERIES_IMX8MQ_M4=y
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CONFIG_SOC_MIMX8MQ6=y
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CONFIG_BOARD_MIMX8MQ_EVK_CM4=y
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CONFIG_CORTEX_M_SYSTICK=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_INTERRUPT_DRIVEN=y
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CONFIG_CONSOLE=y
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CONFIG_XIP=y
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boards/arm/mimx8mq_evk/pinmux.c
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boards/arm/mimx8mq_evk/pinmux.c
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/*
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* Copyright (c) 2021, Kwon Tae-young <tykwon@m2i.co.kr>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <init.h>
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#include <fsl_iomuxc.h>
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static int mimx8mq_evk_pinmux_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart2), okay)
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IOMUXC_SetPinMux(IOMUXC_UART2_RXD_UART2_RX, 0U);
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IOMUXC_SetPinConfig(IOMUXC_UART2_RXD_UART2_RX,
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IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
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IOMUXC_SW_PAD_CTL_PAD_SRE(2U));
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IOMUXC_SetPinMux(IOMUXC_UART2_TXD_UART2_TX, 0U);
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IOMUXC_SetPinConfig(IOMUXC_UART2_TXD_UART2_TX,
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IOMUXC_SW_PAD_CTL_PAD_DSE(6U) |
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IOMUXC_SW_PAD_CTL_PAD_SRE(2U));
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#endif
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return 0;
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}
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SYS_INIT(mimx8mq_evk_pinmux_init, PRE_KERNEL_1, 0);
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