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soc: stm32f3x: clean up after Cube LL clock control

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Following activation of Cube LL based clock control driver,
this commits cleans up the useless structures for RCC definitions
and remove code relative to native F3 Clock control driver.

Change-Id: I6f3ee44adb09adc52927eb4b05f8a829665eb96d
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit is contained in:
Erwan Gouriou 2017-01-25 13:41:38 +01:00 • committed by Maureen Helm
commit c4154fd591
5 changed files with 1 additions and 120 deletions
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89
arch/arm/soc/st_stm32/stm32f3/rcc_registers.h
View file

@ -1,89 +0,0 @@
/*
* Copyright (c) 2016 RnDity Sp. z o.o.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef _STM32F3X_CLOCK_H_
#define _STM32F3X_CLOCK_H_
/**
* @brief Driver for Reset & Clock Control of STM32F3x family processor.
*
* Based on reference manual:
* STM32F303xB.C.D.E advanced ARM ® -based 32-bit MCU
* STM32F334xx advanced ARM ® -based 32-bit MCU
* STM32F37xx advanced ARM ® -based 32-bit MCU
*
* Chapter 8: Reset and clock control (RCC)
*/
/**
* @brief Reset and Clock Control
*/
union __rcc_cr {
uint32_t val;
struct {
uint32_t hsion :1 __packed;
uint32_t hsirdy :1 __packed;
uint32_t rsvd__2 :1 __packed;
uint32_t hsitrim :5 __packed;
uint32_t hsical :8 __packed;
uint32_t hseon :1 __packed;
uint32_t hserdy :1 __packed;
uint32_t hsebyp :1 __packed;
uint32_t csson :1 __packed;
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
uint32_t rsvd__26_31 :6 __packed;
} bit;
};
union __rcc_cfgr {
uint32_t val;
struct {
uint32_t sw :2 __packed;
uint32_t sws :2 __packed;
uint32_t hpre :4 __packed;
uint32_t ppre1 :3 __packed;
uint32_t ppre2 :3 __packed;
uint32_t rsvd__14_15 :2 __packed;
uint32_t pllsrc :1 __packed;
uint32_t pllxtpre :1 __packed;
uint32_t pllmul :4 __packed;
uint32_t rsvd__22_23 :2 __packed;
uint32_t mco :3 __packed;
uint32_t rsvd__27 :1 __packed;
uint32_t mcopre :3 __packed;
uint32_t pllnodiv :1 __packed;
} bit;
};
union __rcc_cfgr2 {
uint32_t val;
struct {
uint32_t prediv :4 __packed;
uint32_t adc12pres : 5 __packed;
uint32_t rsvd__9_31 :23 __packed;
} bit;
};
struct stm32f3x_rcc {
union __rcc_cr cr;
union __rcc_cfgr cfgr;
uint32_t cir;
uint32_t apb2rstr;
uint32_t apb1rstr;
uint32_t ahbenr;
uint32_t apb2enr;
uint32_t apb1enr;
uint32_t bdcr;
uint32_t csr;
uint32_t ahbrstr;
union __rcc_cfgr2 cfgr2;
uint32_t cfgr3;
};
#endif /* _STM32F3X_CLOCK_H_ */

5
arch/arm/soc/st_stm32/stm32f3/soc.c
View file

@ -42,12 +42,9 @@ static int stm32f3_init(struct device *arg)
irq_unlock(key);
/* Update CMSIS SystemCoreClock variable (HCLK) */
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
/* At reset, System core clock is set to 4MHz */
SystemCoreClock = 4000000;
#else
SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
return 0;
}

22
arch/arm/soc/st_stm32/stm32f3/soc_config.c
View file

@ -29,25 +29,3 @@ int stm32_get_pin_config(int pin, int func)
/* encode and return the 'real' alternate function number */
return STM32_PINFUNC(func, STM32F3X_PIN_CONFIG_AF);
}
clock_control_subsys_t stm32_get_port_clock(int port)
{
const clock_control_subsys_t ports_to_clock[STM32_PORTS_MAX] = {
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPA),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPB),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPC),
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPD),
#ifdef CONFIG_SOC_STM32F334X8
UINT_TO_POINTER(0),
#else
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPE),
#endif
UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_IOPF),
};
if (port > STM32_PORTF) {
return NULL;
}
return ports_to_clock[port];
}

4
arch/arm/soc/st_stm32/stm32f3/soc_gpio.c
View file

@ -188,16 +188,12 @@ int stm32_gpio_enable_int(int port, int pin)
struct device *clk =
device_get_binding(STM32_CLOCK_CONTROL_NAME);
#ifdef CONFIG_CLOCK_CONTROL_STM32_CUBE
struct stm32_pclken pclken = {
.bus = STM32_CLOCK_BUS_APB2,
.enr = LL_APB2_GRP1_PERIPH_SYSCFG
};
clock_control_on(clk, (clock_control_subsys_t *) &pclken);
#else
clock_control_on(clk, UINT_TO_POINTER(STM32F3X_CLOCK_SUBSYS_SYSCFG));
#endif /* CONFIG_CLOCK_CONTROL_STM32_CUBE */
int shift = 0;

1
arch/arm/soc/st_stm32/stm32f3/soc_registers.h
View file

@ -8,7 +8,6 @@
#define _STM32F3X_SOC_REGISTERS_H_
/* include register mapping headers */
#include "rcc_registers.h"
#include "flash_registers.h"
#include "gpio_registers.h"