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tests: drivers: clock control for the stm32H5 serie core

Browse source 
Adds the configurations for testing the clock controller driver
of the stm32H5 serie coreon stm32h573i disco kit

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu 2022-12-06 10:12:05 +01:00 • committed by Carles Cufí
commit c3e9879d95
20 changed files with 705 additions and 0 deletions
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9
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/CMakeLists.txt Normal file
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# SPDX-License-Identifier: Apache-2.0
cmake_minimum_required(VERSION 3.20.0)
find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
project(stm32_clock_configuration_h5)
FILE(GLOB app_sources src/*.c)
target_sources(app PRIVATE ${app_sources})

60
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/clear_clocks.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay clears clocks back to a state equivalent to what could
* be found in stm32h5.dtsi
*/
&clk_hse {
status = "disabled";
/delete-property/ clock-frequency;
/delete-property/ hse-bypass;
};
&clk_hsi {
status = "disabled";
/delete-property/ hsi-div;
};
&clk_lse {
status = "disabled";
};
&clk_csi {
status = "disabled";
};
&pll {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&pll2 {
/delete-property/ div-m;
/delete-property/ mul-n;
/delete-property/ div-p;
/delete-property/ div-q;
/delete-property/ div-r;
/delete-property/ clocks;
status = "disabled";
};
&rcc {
/delete-property/ clocks;
/delete-property/ clock-frequency;
/delete-property/ ahb-prescaler;
/delete-property/ apb1-prescaler;
/delete-property/ apb2-prescaler;
/delete-property/ apb3-prescaler;
};

24
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/csi4.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay";
};
&rcc {
clocks = <&clk_csi>;
clock-frequency = <DT_FREQ_M(4)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

30
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hse24.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available nucleo_h503rb
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(24)>;
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(24)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

31
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hse25.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available stm32h573 disco kit
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(25)>;
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
status = "okay";
};
&rcc {
clocks = <&clk_hse>;
clock-frequency = <DT_FREQ_M(25)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

25
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/hsi_32.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <2>; /* HSI RC: 64MHz, hsi_clk = 32MHz */
status = "okay";
};
&rcc {
clocks = <&clk_hsi>;
clock-frequency = <DT_FREQ_M(32)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay";
};
/* Test another couple of M-div N-mul to obtain 100MHz from the CSI */
&pll {
div-m = <1>;
mul-n = <50>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_csi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_240.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay";
};
/* Test another couple of M-div N-mul to obtain 240MHz from the CSI */
&pll {
div-m = <1>;
mul-n = <120>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_csi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

34
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_csi_ahb_2_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_csi {
status = "okay";
};
&pll {
div-m = <1>;
mul-n = <100>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_csi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
clock-frequency = <DT_FREQ_M(100)>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

40
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse24_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available nucleo_h503rb
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(24)>;
};
&pll {
div-m = <6>;
mul-n = <50>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

40
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse24_240.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available nucleo_h503rb
*/
&clk_hse {
status = "okay";
clock-frequency = <DT_FREQ_M(24)>;
};
&pll {
div-m = <2>;
mul-n = <40>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse24_ahb_2_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
clock-frequency = <DT_FREQ_M(24)>;
status = "okay";
};
&pll {
div-m = <6>;
mul-n = <100>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
clock-frequency = <DT_FREQ_M(100)>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

41
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse25_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available stm32h573 disco kit
*/
&clk_hse {
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <2>;
mul-n = <32>;
div-p = <4>;
div-q = <4>;
div-r = <4>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

41
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse25_240.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
/*
* Warning: HSE frequency differs on available boards, hence:
* This configuration is only available stm32h573 disco kit
*/
&clk_hse {
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
status = "okay";
clock-frequency = <DT_FREQ_M(25)>;
};
&pll1 {
div-m = <5>;
mul-n = <96>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

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tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hse25_ahb_2_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hse {
hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
clock-frequency = <DT_FREQ_M(25)>;
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <64>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};
&rcc {
clocks = <&pll>;
ahb-prescaler = <2>; /* Use AHB prescaler to reduce HCLK */
clock-frequency = <DT_FREQ_M(100)>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hsi_100.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
status = "okay";
};
&pll {
div-m = <4>;
mul-n = <50>;
div-p = <4>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(100)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

35
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/pll_hsi_240.overlay Normal file
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/*
* Copyright (c) 2021 Linaro Limited
* Copyright (c) 2023 STMicroelectronics
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Warning: This overlay performs configuration from clean sheet.
* It is assumed that it is applied after clear_clocks.overlay file.
*/
&clk_hsi {
hsi-div = <1>; /* HSI RC: 64MHz, hsi_clk = 64MHz */
status = "okay";
};
&pll {
div-m = <8>;
mul-n = <120>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hsi>;
status = "okay";
};
&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(240)>;
ahb-prescaler = <1>;
apb1-prescaler = <1>;
apb2-prescaler = <1>;
apb3-prescaler = <1>;
};

2
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/prj.conf Normal file
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CONFIG_ZTEST=y
CONFIG_ZTEST_NEW_API=y

79
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/src/test_stm32_clock_configuration.c Normal file
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/*
* Copyright (c) 2021 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/ztest.h>
#include <soc.h>
#include <zephyr/drivers/clock_control.h>
#include <zephyr/drivers/clock_control/stm32_clock_control.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(test);
ZTEST(stm32_syclck_config, test_hclk_freq)
{
uint32_t soc_hclk_freq;
soc_hclk_freq = HAL_RCC_GetHCLKFreq();
zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq,
"Expected hclk_freq: %d. Actual hclk_freq: %d",
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, soc_hclk_freq);
}
ZTEST(stm32_syclck_config, test_sysclk_src)
{
int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
#if STM32_SYSCLK_SRC_PLL
zassert_equal(RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src,
"Expected sysclk src: PLL1 (0x%x). Actual: 0x%x",
RCC_SYSCLKSOURCE_STATUS_PLLCLK, sys_clk_src);
#elif STM32_SYSCLK_SRC_HSE
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
"Expected sysclk src: HSE (0x%x). Actual: 0x%x",
RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src);
#elif STM32_SYSCLK_SRC_HSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
"Expected sysclk src: HSI (0x%x). Actual: 0x%x",
RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src);
#elif STM32_SYSCLK_SRC_CSI
zassert_equal(RCC_SYSCLKSOURCE_STATUS_CSI, sys_clk_src,
"Expected sysclk src: MSI (0x%x). Actual: 0x%x",
RCC_SYSCLKSOURCE_STATUS_CSI, sys_clk_src);
#else
/* Case not expected */
zassert_true((STM32_SYSCLK_SRC_PLL ||
STM32_SYSCLK_SRC_HSE ||
STM32_SYSCLK_SRC_HSI ||
STM32_SYSCLK_SRC_CSI),
"Not expected. sys_clk_src: %d\n", sys_clk_src);
#endif
}
ZTEST(stm32_syclck_config, test_pll_src)
{
uint32_t pll_src = __HAL_RCC_GET_PLL_OSCSOURCE();
#if STM32_PLL_SRC_HSE
zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
"Expected PLL src: HSE. Actual PLL src: %d",
pll_src);
#elif STM32_PLL_SRC_HSI
zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
"Expected PLL src: HSI. Actual PLL src: %d",
pll_src);
#elif STM32_PLL_SRC_CSI
zassert_equal(RCC_PLLSOURCE_CSI, pll_src,
"Expected PLL src: CSI. Actual PLL src: %d",
pll_src);
#else
zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
"Expected PLL src: None. Actual PLL src: %d",
pll_src);
#endif
}
ZTEST_SUITE(stm32_syclck_config, NULL, NULL, NULL, NULL, NULL);

38
tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/testcase.yaml Normal file
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common:
timeout: 5
tags: clock_control
tests:
drivers.stm32_clock_configuration.h5.sysclksrc_pll_csi_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_csi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hsi_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hsi_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hse25_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_pll_hse25_240:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_240.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_csi4:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/csi4.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_hsi_32:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_32.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.sysclksrc_hse_25:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse25.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.pll_csi_ahb_2_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_csi_ahb_2_100.overlay"
platform_allow: stm32h573i_dk
drivers.stm32_clock_configuration.h5.pll_hse25_ahb_2_100:
extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse25_ahb_2_100.overlay"
platform_allow: stm32h573i_dk