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soc: intel_s1000: add DMIC power control

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Add DMIC power on to SoC init sequence

Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
This commit is contained in:
Sathish Kuttan 2018-11-29 16:12:27 -08:00 • committed by Anas Nashif
commit c3da9238f1
2 changed files with 26 additions and 5 deletions
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21
soc/xtensa/intel_s1000/soc.c
View file

@ -186,12 +186,23 @@ u32_t soc_get_ref_clk_freq(void)
static void soc_set_power_and_clock(void) static void soc_set_power_and_clock(void)
{ {
volatile struct soc_dsp_shim_regs *regs = volatile struct soc_dsp_shim_regs *dsp_shim_regs =
(volatile struct soc_dsp_shim_regs *) (volatile struct soc_dsp_shim_regs *)SOC_DSP_SHIM_REG_BASE;
SOC_DSP_SHIM_REG_BASE; #if (CONFIG_AUDIO_INTEL_DMIC)
volatile struct soc_dmic_shim_regs *dmic_shim_regs =
(volatile struct soc_dmic_shim_regs *)SOC_DMIC_SHIM_REG_BASE;
regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK | SOC_CLKCTL_OCS_FAST_CLK; /* enable power */
regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 | dmic_shim_regs->dmiclctl |= SOC_DMIC_SHIM_DMICLCTL_SPA;
while ((dmic_shim_regs->dmiclctl & SOC_DMIC_SHIM_DMICLCTL_CPA) == 0) {
/* wait for power status */
}
#endif
dsp_shim_regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK |
SOC_CLKCTL_OCS_FAST_CLK;
dsp_shim_regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
SOC_PWRCTL_DISABLE_PWR_GATING_DSP0; SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
} }

10
soc/xtensa/intel_s1000/soc.h
View file

@ -117,6 +117,16 @@ struct soc_resource_alloc_regs {
u32_t geno; u32_t geno;
}; };
/* DMIC SHIM Registers */
#define SOC_DMIC_SHIM_REG_BASE 0x00071E80
#define SOC_DMIC_SHIM_DMICLCTL_SPA BIT(0)
#define SOC_DMIC_SHIM_DMICLCTL_CPA BIT(8)
struct soc_dmic_shim_regs {
u32_t dmiclcap;
u32_t dmiclctl;
};
/* SOC DSP SHIM Registers */ /* SOC DSP SHIM Registers */
#define SOC_DSP_SHIM_REG_BASE 0x00071F00 #define SOC_DSP_SHIM_REG_BASE 0x00071F00
/* SOC DSP SHIM Register - Clock Control */ /* SOC DSP SHIM Register - Clock Control */