diff --git a/soc/arm/nuvoton_npcx/common/reg/reg_def.h b/soc/arm/nuvoton_npcx/common/reg/reg_def.h
index dd3d28fb663..dc876320755 100644
--- a/soc/arm/nuvoton_npcx/common/reg/reg_def.h
+++ b/soc/arm/nuvoton_npcx/common/reg/reg_def.h
@@ -226,6 +226,13 @@ static inline uint32_t npcx_lv_gpio_ctl_offset(uint32_t ctl_no)
 #define NPCX_DEVPU0_I2C3_0_PUE                6
 #define NPCX_DEVPU1_F_SPI_PUD_EN              7
 
+/* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
+enum npcx_hif_type {
+	NPCX_HIF_TYPE_NONE,
+	NPCX_HIF_TYPE_LPC,
+	NPCX_HIF_TYPE_ESPI_SHI,
+};
+
 /*
  * System Glue (GLUE) device registers
  */
diff --git a/soc/arm/nuvoton_npcx/common/scfg.c b/soc/arm/nuvoton_npcx/common/scfg.c
index f35967d9d5c..cfdd70b4353 100644
--- a/soc/arm/nuvoton_npcx/common/scfg.c
+++ b/soc/arm/nuvoton_npcx/common/scfg.c
@@ -209,6 +209,13 @@ void npcx_pinctrl_psl_input_configure(void)
 	}
 }
 
+void npcx_host_interface_sel(enum npcx_hif_type hif_type)
+{
+	struct scfg_reg *inst_scfg = HAL_SFCG_INST();
+
+	SET_FIELD(inst_scfg->DEVCNT, NPCX_DEVCNT_HIF_TYP_SEL_FIELD, hif_type);
+}
+
 /* Pin-control driver registration */
 static int npcx_scfg_init(const struct device *dev)
 {
diff --git a/soc/arm/nuvoton_npcx/common/soc_pins.h b/soc/arm/nuvoton_npcx/common/soc_pins.h
index ecde8777282..53002daebf9 100644
--- a/soc/arm/nuvoton_npcx/common/soc_pins.h
+++ b/soc/arm/nuvoton_npcx/common/soc_pins.h
@@ -168,6 +168,13 @@ void npcx_lvol_suspend_io_pads(void);
  */
 bool npcx_lvol_is_enabled(int port, int pin);
 
+/**
+ * @brief Select the host interface type
+ *
+ * @param hif_type host interface type
+ */
+void npcx_host_interface_sel(enum npcx_hif_type hif_type);
+
 #ifdef __cplusplus
 }
 #endif