diff --git a/arch/arm/core/cortex_a_r/__aeabi_read_tp.S b/arch/arm/core/cortex_a_r/__aeabi_read_tp.S
index 25e240b39d3..40874c4a1fa 100644
--- a/arch/arm/core/cortex_a_r/__aeabi_read_tp.S
+++ b/arch/arm/core/cortex_a_r/__aeabi_read_tp.S
@@ -11,5 +11,8 @@ _ASM_FILE_PROLOGUE
 GTEXT(__aeabi_read_tp)
 
 SECTION_FUNC(text, __aeabi_read_tp)
-	mrc 15, 0, r0, c13, c0, 3
+	/*
+	 * TPIDRURW will be used as a base pointer point to TLS aera.
+	 */
+	mrc 15, 0, r0, c13, c0, 2
 	bx lr
diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S
index c646e70cc7e..0031148cae9 100644
--- a/arch/arm/core/cortex_a_r/swap_helper.S
+++ b/arch/arm/core/cortex_a_r/swap_helper.S
@@ -121,10 +121,10 @@ out_fp_inactive:
     ldr r0, [r4]
 
     /* Store TLS pointer in the "Process ID" register.
-     * This register is used as a base pointer to all
+     * TPIDRURW is used as a base pointer to all
      * thread variables with offsets added by toolchain.
      */
-    mcr 15, 0, r0, cr13, cr0, 3
+    mcr 15, 0, r0, c13, c0, 2
 #endif
 
 #if defined(CONFIG_ARM_STORE_EXC_RETURN)
diff --git a/cmake/compiler/gcc/target_arm.cmake b/cmake/compiler/gcc/target_arm.cmake
index 0cfaba43da0..a813c2563a3 100644
--- a/cmake/compiler/gcc/target_arm.cmake
+++ b/cmake/compiler/gcc/target_arm.cmake
@@ -34,5 +34,10 @@ if(CONFIG_FP16)
     list(APPEND ARM_C_FLAGS   -mfp16-format=alternative)
   endif()
 endif()
+
+if(CONFIG_THREAD_LOCAL_STORAGE)
+    list(APPEND ARM_C_FLAGS -mtp=soft)
+endif()
+
 list(APPEND TOOLCHAIN_C_FLAGS ${ARM_C_FLAGS})
 list(APPEND TOOLCHAIN_LD_FLAGS NO_SPLIT ${ARM_C_FLAGS})