drivers: intc_ite_it8xxx2: disable debug mode then reset for tests
After flashed EC image, we needed to manually press the reset button on it8xxx2_evb. Now, without pressing the button, we can disable debug mode and trigger a watchdog hard reset for running tests. After flash EC, running below tests can pass (without pressing the button): west build -p always -b it8xxx2_evb tests/drivers/watchdog/wdt_basic_api west build -p always -b it8xxx2_evb tests/kernel/timer/timer_api west build -p always -b it8xxx2_evb tests/kernel/fatal/exception Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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2 changed files with 40 additions and 2 deletions
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@ -250,6 +250,37 @@ static void intc_irq0_handler(const void *arg)
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void soc_interrupt_init(void)
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void soc_interrupt_init(void)
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{
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{
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#ifdef CONFIG_ZTEST
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/*
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* After flashed EC image, we needed to manually press the reset button
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* on it8xxx2_evb, then run the test. Now, without pressing the button,
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* we can disable debug mode and trigger a watchdog hard reset then
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* run tests.
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*/
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struct wdt_it8xxx2_regs *const wdt_regs = WDT_IT8XXX2_REGS_BASE;
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struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
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if (gctrl_regs->GCTRL_DBGROS & IT8XXX2_GCTRL_SMB_DBGR) {
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/* Disable debug mode through i2c */
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IT8XXX2_SMB_SLVISELR |= BIT(4);
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/* Enable ETWD reset */
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wdt_regs->ETWCFG = 0;
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wdt_regs->ET1PSR = IT8XXX2_WDT_ETPS_1P024_KHZ;
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wdt_regs->ETWCFG = (IT8XXX2_WDT_EWDKEYEN | IT8XXX2_WDT_EWDSRC);
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/* Enable ETWD hardware reset */
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gctrl_regs->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN;
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/* Trigger ETWD reset */
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wdt_regs->EWDKEYR = 0;
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/* Spin and wait for reboot */
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while (1)
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;
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} else {
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/* Disable ETWD hardware reset */
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gctrl_regs->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN;
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}
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#endif
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/* Ensure interrupts of soc are disabled at default */
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/* Ensure interrupts of soc are disabled at default */
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for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
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for (int i = 0; i < ARRAY_SIZE(reg_enable); i++)
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*reg_enable[i] = 0;
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*reg_enable[i] = 0;
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@ -347,6 +347,9 @@ struct kscan_it8xxx2_regs {
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* (1Fxxh) External Timer & External Watchdog (ETWD)
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* (1Fxxh) External Timer & External Watchdog (ETWD)
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*
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*
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*/
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*/
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#define WDT_IT8XXX2_REGS_BASE \
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((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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struct wdt_it8xxx2_regs {
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struct wdt_it8xxx2_regs {
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/* 0x000: Reserved1 */
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/* 0x000: Reserved1 */
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@ -1542,8 +1545,10 @@ struct gctrl_it8xxx2_regs {
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volatile uint8_t reserved_00_01[2];
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volatile uint8_t reserved_00_01[2];
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/* 0x02: Chip Version */
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/* 0x02: Chip Version */
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volatile uint8_t GCTRL_ECHIPVER;
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volatile uint8_t GCTRL_ECHIPVER;
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/* 0x03-0x05: Reserved_03_05 */
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/* 0x03: DBGR Operate Status */
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volatile uint8_t reserved_03_05[3];
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volatile uint8_t GCTRL_DBGROS;
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/* 0x04-0x05: Reserved_04_05 */
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volatile uint8_t reserved_04_05[2];
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/* 0x06: Reset Status */
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/* 0x06: Reset Status */
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volatile uint8_t GCTRL_RSTS;
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volatile uint8_t GCTRL_RSTS;
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/* 0x07-0x09: Reserved_07_09 */
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/* 0x07-0x09: Reserved_07_09 */
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@ -1630,6 +1635,8 @@ struct gctrl_it8xxx2_regs {
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#endif /* !__ASSEMBLER__ */
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#endif /* !__ASSEMBLER__ */
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/* GCTRL register fields */
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/* GCTRL register fields */
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/* 0x03: DBGR Operate Status */
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#define IT8XXX2_GCTRL_SMB_DBGR BIT(0)
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/* 0x06: Reset Status */
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/* 0x06: Reset Status */
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#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0))
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#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0))
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#define IT8XXX2_GCTRL_IWDTR BIT(1)
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#define IT8XXX2_GCTRL_IWDTR BIT(1)
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