drivers: adc: stm32: fix f3x series
The patch fixes driver compile errors and ADC management for the f3x series. It was developed and tested for the stm32f373 variant. Tested-by: Dario Binacchi <dariobin@libero.it> Signed-off-by: Dario Binacchi <dariobin@libero.it>
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c32a96af6a
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c3a067e841
1 changed files with 34 additions and 12 deletions
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@ -28,6 +28,14 @@ LOG_MODULE_REGISTER(adc_stm32);
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <pinmux/pinmux_stm32.h>
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#if defined(CONFIG_SOC_SERIES_STM32F3X)
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#if defined(ADC1_V2_5)
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#define STM32F3X_ADC_V2_5
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#elif defined(ADC5_V1_1)
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#define STM32F3X_ADC_V1_1
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#endif
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#endif
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#if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
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!defined(CONFIG_SOC_SERIES_STM32G0X) && \
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!defined(CONFIG_SOC_SERIES_STM32L0X) && \
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@ -75,7 +83,8 @@ static const uint32_t table_seq_len[] = {
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#define RES(n) LL_ADC_RESOLUTION_##n##B
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static const uint32_t table_resolution[] = {
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(STM32F3X_ADC_V2_5)
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RES(12),
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#elif !defined(CONFIG_SOC_SERIES_STM32H7X)
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RES(6),
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@ -281,6 +290,7 @@ static void adc_stm32_start_conversion(const struct device *dev)
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!defined(CONFIG_SOC_SERIES_STM32F4X) && \
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!defined(CONFIG_SOC_SERIES_STM32F7X) && \
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!defined(CONFIG_SOC_SERIES_STM32F1X) && \
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!defined(STM32F3X_ADC_V2_5) && \
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!defined(CONFIG_SOC_SERIES_STM32L1X)
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static void adc_stm32_calib(const struct device *dev)
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{
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@ -288,7 +298,7 @@ static void adc_stm32_calib(const struct device *dev)
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(const struct adc_stm32_cfg *)dev->config;
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ADC_TypeDef *adc = config->base;
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
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#if defined(STM32F3X_ADC_V1_1) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G4X)
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@ -316,7 +326,8 @@ static int start_read(const struct device *dev,
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int err;
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switch (sequence->resolution) {
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#if defined(CONFIG_SOC_SERIES_STM32F1X)
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(STM32F3X_ADC_V2_5)
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case 12:
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resolution = table_resolution[0];
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break;
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@ -409,7 +420,8 @@ static int start_read(const struct device *dev,
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LL_ADC_Enable(adc);
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while (LL_ADC_IsActiveFlag_ADRDY(adc) != 1UL) {
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}
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#elif !defined(CONFIG_SOC_SERIES_STM32F1X)
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#elif !defined(CONFIG_SOC_SERIES_STM32F1X) && \
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!defined(STM32F3X_ADC_V2_5)
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LL_ADC_SetResolution(adc, resolution);
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#endif
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@ -418,6 +430,7 @@ static int start_read(const struct device *dev,
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!defined(CONFIG_SOC_SERIES_STM32F4X) && \
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!defined(CONFIG_SOC_SERIES_STM32F7X) && \
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!defined(CONFIG_SOC_SERIES_STM32F1X) && \
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!defined(STM32F3X_ADC_V2_5) && \
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!defined(CONFIG_SOC_SERIES_STM32L1X)
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adc_stm32_calib(dev);
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#else
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@ -427,7 +440,7 @@ static int start_read(const struct device *dev,
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}
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(STM32F3X_ADC_V1_1) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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@ -438,6 +451,9 @@ static int start_read(const struct device *dev,
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LL_ADC_EnableIT_EOC(adc);
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#elif defined(CONFIG_SOC_SERIES_STM32F1X)
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LL_ADC_EnableIT_EOS(adc);
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#elif defined(STM32F3X_ADC_V2_5)
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LL_ADC_Enable(adc);
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LL_ADC_EnableIT_EOS(adc);
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#else
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LL_ADC_EnableIT_EOCS(adc);
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#endif
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@ -674,13 +690,14 @@ static int adc_stm32_init(const struct device *dev)
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* mode, and restore its calibration parameters if there are some
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* previously stored calibration parameters.
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*/
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LL_ADC_DisableDeepPowerDown(adc);
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#endif
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/*
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* F3, L4, WB, G0 and G4 ADC modules need some time
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* to be stabilized before performing any enable or calibration actions.
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*/
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#if defined(CONFIG_SOC_SERIES_STM32F3X) || \
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#if defined(STM32F3X_ADC_V1_1) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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@ -695,7 +712,7 @@ static int adc_stm32_init(const struct device *dev)
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32WLX)
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LL_ADC_SetClock(adc, LL_ADC_CLOCK_SYNC_PCLK_DIV4);
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#elif defined(CONFIG_SOC_SERIES_STM32F3X) || \
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#elif defined(STM32F3X_ADC_V1_1) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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defined(CONFIG_SOC_SERIES_STM32G0X) || \
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@ -712,10 +729,11 @@ static int adc_stm32_init(const struct device *dev)
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!defined(CONFIG_SOC_SERIES_STM32F4X) && \
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!defined(CONFIG_SOC_SERIES_STM32F7X) && \
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!defined(CONFIG_SOC_SERIES_STM32F1X) && \
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!defined(STM32F3X_ADC_V2_5) && \
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!defined(CONFIG_SOC_SERIES_STM32L1X)
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/*
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* Calibration of F1 series has to be started after ADC Module is
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* enabled.
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* Calibration of F1 and F3 (ADC1_V2_5) series has to be started
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* after ADC Module is enabled.
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*/
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adc_stm32_calib(dev);
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#endif
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@ -741,7 +759,7 @@ static int adc_stm32_init(const struct device *dev)
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#endif
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#if defined(CONFIG_SOC_SERIES_STM32F0X) || \
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defined(CONFIG_SOC_SERIES_STM32F3X) || \
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defined(STM32F3X_ADC_V1_1) || \
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defined(CONFIG_SOC_SERIES_STM32L0X) || \
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defined(CONFIG_SOC_SERIES_STM32L4X) || \
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defined(CONFIG_SOC_SERIES_STM32WBX) || \
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@ -795,8 +813,12 @@ static int adc_stm32_init(const struct device *dev)
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config->irq_cfg_func();
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#ifdef CONFIG_SOC_SERIES_STM32F1X
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/* Calibration of F1 must starts after two cycles after ADON is set. */
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#if defined(CONFIG_SOC_SERIES_STM32F1X) || \
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defined(STM32F3X_ADC_V2_5)
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/*
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* Calibration of F1 and F3 (ADC1_V2_5) must starts after two cycles
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* after ADON is set.
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*/
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LL_ADC_StartCalibration(adc);
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LL_ADC_REG_SetTriggerSource(adc, LL_ADC_REG_TRIG_SOFTWARE);
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#endif
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