doc: interrupts: add documentation section for zero-latency IRQs
Add a simple documentation section for the Zero-Latency IRQs feature supported by the kernel. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
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@ -152,6 +152,32 @@ The IRQ must be subsequently **enabled** to permit the ISR to execute.
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Disabling an IRQ prevents *all* threads in the system from being preempted
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by the associated ISR, not just the thread that disabled the IRQ.
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Zero Latency Interrupts
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-----------------------
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Preventing interruptions by applying an IRQ lock may increase the observed
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interrupt latency. A high interrupt latency, however, may not be acceptable
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for certain low-latency use-cases.
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The kernel addresses such use-cases by allowing interrupts with critical
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latency constraints to execute at a priority level that cannot be blocked
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by interrupt locking. These interrupts are defined as
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*zero-latency interrupts*. The support for zero-latency interrupts requires
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:option:`CONFIG_ZERO_LATENCY_IRQS` to be enabled.
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Zero-latency interrupts are expected to be used to manage hardware events
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directly, and not to interoperate with the kernel code at all. They should
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treat all kernel APIs as undefined behavior (i.e. an application that uses the
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APIs inside a zero-latency interrupt context is responsible for directly
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verifying correct behavior). Zero-latency interrupts may not modify any data
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inspected by kernel APIs invoked from normal Zephyr contexts and shall not
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generate exceptions that need to be handled synchronously (e.g. kernel panic).
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.. important::
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Zero-latency interrupts are supported on an architecture-specific basis.
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The feature is currently implemented in the ARM Cortex-M architecture
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variant.
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Offloading ISR Work
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===================
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