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boards: mec1501modular: Enable additional drivers for modular MEC1501

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Enable PWM, ADC, KSCAN and PS2 drivers
Make VCI capable pins to GPIO mode

Signed-off-by: Jose Alberto Meza <jose.a.meza.arellano@intel.com>
This commit is contained in:
Jose Alberto Meza 2019-12-13 15:28:29 -08:00 • committed by Andrew Boie
commit c31c6aa99d
7 changed files with 166 additions and 5 deletions
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6
boards/arm/mec1501modular_assy6885/CMakeLists.txt
View file

@ -8,9 +8,7 @@ zephyr_library()
zephyr_library_sources(pinmux.c)
if(DEFINED ENV{EVERGLADES_SPI_GEN})
# Check if location for MCHP tool is defined.
# This tool generates a binary image to flash the SPI chip.
# See board documentation for further details on this.
# Grab it from environment variable if defined
set(EVERGLADES_SPI_GEN $ENV{EVERGLADES_SPI_GEN})
else()
# Else find the tool in PATH
@ -47,7 +45,7 @@ if(DEFINED EVERGLADES_SPI_GEN)
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
COMMAND ${EVERGLADES_SPI_GEN}
-i ${EVERGLADES_SPI_CFG}
-o ${PROJECT_BINARY_DIR}/spi_image.bin
-o ${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}
)
unset(EVERGLADES_SPI_GEN)

14
boards/arm/mec1501modular_assy6885/Kconfig.defconfig
View file

@ -32,7 +32,7 @@ config PINMUX_XEC_GPIO200_236
default n
config PINMUX_XEC_GPIO240_276
default n
default y
endif # PINMUX_XEC
@ -116,4 +116,16 @@ config PS2_XEC_1
default y
endif # PS2
# power management stuff
if SYS_POWER_MANAGEMENT
config SYS_PM_MIN_RESIDENCY_SLEEP_1
default 1000
config SYS_PM_MIN_RESIDENCY_DEEP_SLEEP_1
default 2000
endif # SYS_POWER_MANAGEMENT
endif # BOARD_MEC1501MODULAR_ASSY6885

11
boards/arm/mec1501modular_assy6885/board.cmake Normal file
View file

@ -0,0 +1,11 @@
# SPDX-License-Identifier: Apache-2.0
set(SPI_IMAGE_NAME spi_image.bin)
board_set_flasher_ifnset(dediprog)
# --vcc=0 - use 3.5V to flash
board_finalize_runner_args(dediprog
"--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
"--vcc=0"
)

4
boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.dts
View file

@ -66,3 +66,7 @@
&pwm0 {
status = "okay";
};
&kscan0 {
status = "okay";
};

2
boards/arm/mec1501modular_assy6885/mec1501modular_assy6885.yaml
View file

@ -22,3 +22,5 @@ supported:
- pinmux
- pwm
- watchdog
- ps2
- kscan

6
boards/arm/mec1501modular_assy6885/mec1501modular_assy6885_defconfig
View file

@ -18,7 +18,13 @@ CONFIG_SERIAL=y
CONFIG_PINMUX=y
CONFIG_GPIO=y
CONFIG_PS2=y
CONFIG_KSCAN=y
CONFIG_ADC=y
CONFIG_PWM=y
CONFIG_I2C=y
CONFIG_I2C_INIT_PRIORITY=60
CONFIG_ESPI=y
CONFIG_ESPI_PERIPHERAL_UART_SOC_MAPPING=1
CONFIG_SOC_POWER_MANAGEMENT=y

128
boards/arm/mec1501modular_assy6885/pinmux.c
View file

@ -54,6 +54,15 @@ static int board_pinmux_init(struct device *dev)
ECS_REGS->DEBUG_CTRL = (MCHP_ECS_DCTRL_DBG_EN |
MCHP_ECS_DCTRL_MODE_SWD);
/* Configure pins that are not GPIOS by default */
pinmux_pin_set(porta, MCHP_GPIO_000, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portd, MCHP_GPIO_161, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portd, MCHP_GPIO_162, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portd, MCHP_GPIO_163, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portd, MCHP_GPIO_170, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portd, MCHP_GPIO_172, MCHP_GPIO_CTRL_MUX_F0);
pinmux_pin_set(portf, MCHP_GPIO_250, MCHP_GPIO_CTRL_MUX_F0);
/* See table 2-4 from the data sheet for pin multiplexing*/
#ifdef CONFIG_UART_NS16550_PORT_1
/* Set muxing, for UART 1 TX/RX and power up */
@ -72,6 +81,7 @@ static int board_pinmux_init(struct device *dev)
mchp_pcr_periph_slp_ctrl(PCR_ADC, MCHP_PCR_SLEEP_DIS);
/* ADC pin muxes, ADC00 - ADC07 */
/* Note, by default ETM is enabled ADC00-ADC03 are not available */
pinmux_pin_set(porte, MCHP_GPIO_200, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_201, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_202, MCHP_GPIO_CTRL_MUX_F1);
@ -185,6 +195,124 @@ static int board_pinmux_init(struct device *dev)
#endif
#endif /* CONFIG_PWM_XEC */
#if defined CONFIG_KSCAN_XEC
/* KSCAN KSO00 */
pinmux_pin_set(portb, MCHP_GPIO_040,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO01 */
pinmux_pin_set(portb, MCHP_GPIO_045,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO02 */
pinmux_pin_set(portb, MCHP_GPIO_046,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO012 */
pinmux_pin_set(portc, MCHP_GPIO_125,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO013 */
pinmux_pin_set(portc, MCHP_GPIO_126,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO03 */
pinmux_pin_set(portb, MCHP_GPIO_047,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO04 */
pinmux_pin_set(portc, MCHP_GPIO_107,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO05 */
pinmux_pin_set(portc, MCHP_GPIO_112,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO06 */
pinmux_pin_set(portc, MCHP_GPIO_113,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO14 */
pinmux_pin_set(portd, MCHP_GPIO_152,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO15 */
pinmux_pin_set(portd, MCHP_GPIO_151,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO07 */
pinmux_pin_set(portc, MCHP_GPIO_120,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO08 */
pinmux_pin_set(portc, MCHP_GPIO_121,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO09 */
pinmux_pin_set(portc, MCHP_GPIO_122,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO10 */
pinmux_pin_set(portc, MCHP_GPIO_123,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSO11 */
pinmux_pin_set(portc, MCHP_GPIO_124,
MCHP_GPIO_CTRL_MUX_F2 | MCHP_GPIO_CTRL_PUD_PU);
/* KSCAN KSI00 */
pinmux_pin_set(porta, MCHP_GPIO_017,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI01 */
pinmux_pin_set(porta, MCHP_GPIO_020,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI02 */
pinmux_pin_set(porta, MCHP_GPIO_021,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI03 */
pinmux_pin_set(porta, MCHP_GPIO_026,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI04 */
pinmux_pin_set(porta, MCHP_GPIO_027,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI05 */
pinmux_pin_set(porta, MCHP_GPIO_030,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI06 */
pinmux_pin_set(porta, MCHP_GPIO_031,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
/* KSCAN KSI07 */
pinmux_pin_set(porta, MCHP_GPIO_032,
MCHP_GPIO_CTRL_MUX_F1 | MCHP_GPIO_CTRL_BUFT_OPENDRAIN);
#endif /* CONFIG_KSCAN_XEC */
#ifdef CONFIG_SPI_XEC_QMSPI
#if defined(DT_INST_0_MICROCHIP_XEC_QMSPI)
mchp_pcr_periph_slp_ctrl(PCR_QMSPI, MCHP_PCR_SLEEP_DIS);
#if DT_SPI_XEC_QMSPI_0_PORT_SEL == 0
/* Port 0: Shared SPI pins. Shared has two chip selects */
#if DT_SPI_XEC_QMSPI_0_CHIP_SELECT == 0
pinmux_pin_set(portb, MCHP_GPIO_055, MCHP_GPIO_CTRL_MUX_F2);
#else
pinmux_pin_set(porta, MCHP_GPIO_002, MCHP_GPIO_CTRL_MUX_F2);
#endif
pinmux_pin_set(portb, MCHP_GPIO_056, MCHP_GPIO_CTRL_MUX_F2);
pinmux_pin_set(porte, MCHP_GPIO_223, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porte, MCHP_GPIO_224, MCHP_GPIO_CTRL_MUX_F2);
#if DT_SPI_XEC_QMSPI_0_LINES == 4
pinmux_pin_set(porte, MCHP_GPIO_227, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(porta, MCHP_GPIO_016, MCHP_GPIO_CTRL_MUX_F2);
#endif
#else
/* Port 1: Private SPI pins. Only one chip select */
pinmux_pin_set(portc, MCHP_GPIO_124, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_125, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_121, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_122, MCHP_GPIO_CTRL_MUX_F1);
#if DT_SPI_XEC_QMSPI_0_LINES == 4
pinmux_pin_set(portc, MCHP_GPIO_123, MCHP_GPIO_CTRL_MUX_F1);
pinmux_pin_set(portc, MCHP_GPIO_126, MCHP_GPIO_CTRL_MUX_F1);
#endif
#endif /* DT_SPI_XEC_QMSPI_0_PORT_SEL == 0 */
#endif /* DT_INST_0_MICROCHIP_XEC_QMSPI */
#endif /* CONFIG_SPI_XEC_QMSPI */
#ifdef CONFIG_SYS_PM_DEBUG
/*
* Deep sleep testing: Enable TEST_CLK_OUT on GPIO_060 function 2.
* TEST_CLK_OUT is the PLL 48MHz conditioned output.
*/
pinmux_pin_set(portb, MCHP_GPIO_060, MCHP_GPIO_CTRL_MUX_F2);
#endif
return 0;
}