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arch: arm: Add Cortex-R support

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This adds initial Cortex-R support for interrupts and context switching.

Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
This commit is contained in:
Bradley Bolen 2018-06-25 09:15:14 -04:00 • committed by Ioannis Glaropoulos
commit c30a71df95
37 changed files with 1516 additions and 82 deletions
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39
arch/arm/core/exc_exit.S
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@ -24,6 +24,9 @@ _ASM_FILE_PROLOGUE
GTEXT(z_ExcExit)
GTEXT(_IntExit)
GDATA(_kernel)
#if defined(CONFIG_CPU_CORTEX_R)
GTEXT(__pendsv)
#endif
/**
*
@ -66,6 +69,9 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
*/
SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_ExcExit)
#if defined(CONFIG_CPU_CORTEX_R)
push {r0, lr}
#endif
#ifdef CONFIG_PREEMPT_ENABLED
ldr r0, =_kernel
@ -76,10 +82,16 @@ SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_ExcExit)
cmp r0, r1
beq _EXIT_EXC
#if defined(CONFIG_CPU_CORTEX_M)
/* context switch required, pend the PendSV exception */
ldr r1, =_SCS_ICSR
ldr r2, =_SCS_ICSR_PENDSV
str r2, [r1]
#elif defined(CONFIG_CPU_CORTEX_R)
push {r0, lr}
bl __pendsv
pop {r0, lr}
#endif
_ExcExitWithGdbStub:
@ -96,4 +108,31 @@ _EXIT_EXC:
pop {r0, lr}
#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
#endif /* CONFIG_STACK_SENTINEL */
#if defined(CONFIG_CPU_CORTEX_M)
bx lr
#elif defined(CONFIG_CPU_CORTEX_R)
/*
* r0-r3 are either the values from the thread before it was switched out
* or they are the args to _new_thread for a new thread
*/
pop {r0, lr}
push {r4, r5}
cmp r0, #RET_FROM_SVC
cps #MODE_SYS
ldmia sp!, {r0-r5}
beq _svc_exit
cps #MODE_IRQ
b _exc_exit
_svc_exit:
cps #MODE_SVC
_exc_exit:
mov r12, r4
mov lr, r5
pop {r4, r5}
movs pc, lr
#endif