gpio: silabs gecko: Add device tree support for GPIO

Convert gpio_gecko driver over to using device tree. Added binding
files, updates to dts for various SoCs that use gpio_gecko.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

drivers/gpio/Kconfig.gecko

@@ -8,81 +8,44 @@
 menuconfig GPIO_GECKO
 	bool "Gecko GPIO driver"
 	depends on GPIO && HAS_SILABS_GECKO
+	select HAS_DTS_GPIO
 	help
 	  Enable the Gecko gpio driver.
 
 if GPIO_GECKO
 
-config GPIO_GECKO_COMMON_NAME
-	string "Common driver name"
-	default "GPIO_COMMON"
-
 config GPIO_GECKO_COMMON_INIT_PRIORITY
 	int "Common initialization priority"
 	default 39
 
-config GPIO_GECKO_COMMON_PRI
-	int "Interrupt priority"
-	default 2
-
 config GPIO_GECKO_PORTA
 	bool "Port A"
 	help
 	  Enable Port A.
 
-config GPIO_GECKO_PORTA_NAME
-	string "Port A driver name"
-	depends on GPIO_GECKO_PORTA
-	default "GPIO_0"
-
 config GPIO_GECKO_PORTB
 	bool "Port B"
 	help
 	  Enable Port B.
 
-config GPIO_GECKO_PORTB_NAME
-	string "Port B driver name"
-	depends on GPIO_GECKO_PORTB
-	default "GPIO_1"
-
 config GPIO_GECKO_PORTC
 	bool "Port C"
 	help
 	  Enable Port C.
 
-config GPIO_GECKO_PORTC_NAME
-	string "Port C driver name"
-	depends on GPIO_GECKO_PORTC
-	default "GPIO_2"
-
 config GPIO_GECKO_PORTD
 	bool "Port D"
 	help
 	  Enable Port D.
 
-config GPIO_GECKO_PORTD_NAME
-	string "Port D driver name"
-	depends on GPIO_GECKO_PORTD
-	default "GPIO_3"
-
 config GPIO_GECKO_PORTE
 	bool "Port E"
 	help
 	  Enable Port E.
 
-config GPIO_GECKO_PORTE_NAME
-	string "Port E driver name"
-	depends on GPIO_GECKO_PORTE
-	default "GPIO_4"
-
 config GPIO_GECKO_PORTF
 	bool "Port F"
 	help
 	  Enable Port F.
 
-config GPIO_GECKO_PORTF_NAME
-	string "Port F driver name"
-	depends on GPIO_GECKO_PORTF
-	default "GPIO_5"
-
 endif # GPIO_GECKO

drivers/gpio/gpio_gecko.c

@@ -294,10 +294,10 @@ DEVICE_AND_API_INIT(gpio_gecko_common, CONFIG_GPIO_GECKO_COMMON_NAME,
 static int gpio_gecko_common_init(struct device *dev)
 {
 	gpio_gecko_common_data.count = 0;
-	IRQ_CONNECT(GPIO_EVEN_IRQn, CONFIG_GPIO_GECKO_COMMON_PRI,
+	IRQ_CONNECT(GPIO_EVEN_IRQn, CONFIG_GPIO_GECKO_COMMON_EVEN_PRI,
 		    gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
 
-	IRQ_CONNECT(GPIO_ODD_IRQn, CONFIG_GPIO_GECKO_COMMON_PRI,
+	IRQ_CONNECT(GPIO_ODD_IRQn, CONFIG_GPIO_GECKO_COMMON_ODD_PRI,
 		    gpio_gecko_common_isr, DEVICE_GET(gpio_gecko_common), 0);
 
 	irq_enable(GPIO_EVEN_IRQn);

dts/arm/silabs/efm32wg.dtsi

@@ -1,4 +1,5 @@
 #include <arm/armv7-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	cpus {
@@ -61,6 +62,66 @@
 			status = "disabled";
 			label = "UART_4";
 		};
+
+		gpio@40006100 {
+			compatible = "silabs,efm32-gpio";
+			reg = <0x40006100 0xf00>;
+			interrupts = <1 2 11 2>;
+			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
+			label = "GPIO";
+
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@40006000 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x40006000 0x24>;
+				label = "GPIO_A";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiob: gpio@40006024 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x40006024 0x24>;
+				label = "GPIO_B";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioc: gpio@40006048 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x40006048 0x24>;
+				label = "GPIO_C";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiod: gpio@4000606c {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x4000606c 0x24>;
+				label = "GPIO_D";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioe: gpio@40006090 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x40006090 0x24>;
+				label = "GPIO_E";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiof: gpio@400060b4 {
+				compatible = "silabs,efm32-gpio-port";
+				reg = <0x400060b4 0x24>;
+				label = "GPIO_F";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
 	};
 };
 

dts/arm/silabs/efr32fg1p.dtsi

@@ -1,4 +1,5 @@
 #include <arm/armv7-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	cpus {
@@ -37,6 +38,66 @@
 			status = "disabled";
 			label = "UART_1";
 		};
+
+		gpio@4000a400 {
+			compatible = "silabs,efr32xg1-gpio";
+			reg = <0x4000a400 0xc00>;
+			interrupts = <9 2 17 2>;
+			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
+			label = "GPIO";
+
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@4000a000 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000a000 0x30>;
+				label = "GPIO_A";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiob: gpio@4000a030 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000a030 0x30>;
+				label = "GPIO_B";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioc: gpio@4000a060 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000a060 0x30>;
+				label = "GPIO_C";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiod: gpio@4000a090 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000a090 0x30>;
+				label = "GPIO_D";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpioe: gpio@4000a0c0 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000a0c0 0x30>;
+				label = "GPIO_E";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+
+			gpiof: gpio@4000a0f0 {
+				compatible = "silabs,efr32xg1-gpio-port";
+				reg = <0x4000af0 0x30>;
+				label = "GPIO_F";
+				gpio-controller;
+				#gpio-cells = <2>;
+			};
+		};
 	};
 };
 

dts/bindings/gpio/silabs,efm32-gpio-port.yaml

@@ -0,0 +1,32 @@
+---
+title: EFM32 GPIO
+id: silabs,efm32-gpio-port
+version: 0.1
+
+description: >
+    This is a representation of the EFM32 GPIO Port nodes
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "silabs,efm32-gpio-port"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+"#cells":
+  - pin
+  - flags
+...

dts/bindings/gpio/silabs,efm32-gpio.yaml

@@ -0,0 +1,35 @@
+---
+title: EFM32 GPIO
+id: silabs,efm32-gpio
+version: 0.1
+
+description: >
+    This is a representation of the EFM32 GPIO nodes
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "silabs,efm32-gpio"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    interrupts:
+      type: compound
+      category: required
+      description: required interrupts
+      generation: define
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+...

dts/bindings/gpio/silabs,efr32xg1-gpio-port.yaml

@@ -0,0 +1,32 @@
+---
+title: EFR32XG1 GPIO
+id: silabs,efr32xg1-gpio-port
+version: 0.1
+
+description: >
+    This is a representation of the EFR32XG1 GPIO Port nodes
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "silabs,efr32xg1-gpio-port"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+"#cells":
+  - pin
+  - flags
+...

dts/bindings/gpio/silabs,efr32xg1-gpio.yaml

@@ -0,0 +1,35 @@
+---
+title: EFR32XG1 GPIO
+id: silabs,efr32xg1-gpio
+version: 0.1
+
+description: >
+    This is a representation of the EFR32XG1 GPIO nodes
+
+properties:
+    compatible:
+      type: string
+      category: required
+      description: compatible strings
+      constraint: "silabs,efr32xg1-gpio"
+      generation: define
+
+    reg:
+      type: int
+      description: mmio register space
+      generation: define
+      category: required
+
+    interrupts:
+      type: compound
+      category: required
+      description: required interrupts
+      generation: define
+
+    label:
+      type: string
+      category: required
+      description: Human readable string describing the device (used by Zephyr for API name)
+      generation: define
+
+...

soc/arm/silabs_exx32/efm32wg/dts_fixup.h

@@ -12,4 +12,17 @@
 #define CONFIG_UART_GECKO_0_BAUD_RATE	SILABS_EFM32_USART_4000C000_CURRENT_SPEED
 #define CONFIG_UART_GECKO_0_IRQ_PRI	SILABS_EFM32_USART_4000C000_IRQ_0_PRIORITY
 
+#define CONFIG_GPIO_GECKO_COMMON_NAME	SILABS_EFM32_GPIO_40006100_LABEL
+#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ	SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN
+#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI	SILABS_EFM32_GPIO_40006100_IRQ_GPIO_EVEN_PRIORITY
+#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ	SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD
+#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI	SILABS_EFM32_GPIO_40006100_IRQ_GPIO_ODD_PRIORITY
+
+#define CONFIG_GPIO_GECKO_PORTA_NAME	SILABS_EFM32_GPIO_PORT_40006000_LABEL
+#define CONFIG_GPIO_GECKO_PORTB_NAME	SILABS_EFM32_GPIO_PORT_40006024_LABEL
+#define CONFIG_GPIO_GECKO_PORTC_NAME	SILABS_EFM32_GPIO_PORT_40006048_LABEL
+#define CONFIG_GPIO_GECKO_PORTD_NAME	SILABS_EFM32_GPIO_PORT_4000606C_LABEL
+#define CONFIG_GPIO_GECKO_PORTE_NAME	SILABS_EFM32_GPIO_PORT_40006090_LABEL
+#define CONFIG_GPIO_GECKO_PORTF_NAME	SILABS_EFM32_GPIO_PORT_400060B4_LABEL
+
 /* End of SoC Level DTS fixup file */

soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h

@@ -12,4 +12,17 @@
 #define CONFIG_USART_GECKO_0_BAUD_RATE	SILABS_EFM32_USART_40010000_CURRENT_SPEED
 #define CONFIG_USART_GECKO_0_IRQ_PRI	SILABS_EFM32_USART_40010000_IRQ_0_PRIORITY
 
+#define CONFIG_GPIO_GECKO_COMMON_NAME	SILABS_EFR32XG1_GPIO_4000A400_LABEL
+#define CONFIG_GPIO_GECKO_COMMON_EVEN_IRQ	SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN
+#define CONFIG_GPIO_GECKO_COMMON_EVEN_PRI	SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_EVEN_PRIORITY
+#define CONFIG_GPIO_GECKO_COMMON_ODD_IRQ	SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD
+#define CONFIG_GPIO_GECKO_COMMON_ODD_PRI	SILABS_EFR32XG1_GPIO_4000A400_IRQ_GPIO_ODD_PRIORITY
+
+#define CONFIG_GPIO_GECKO_PORTA_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A000_LABEL
+#define CONFIG_GPIO_GECKO_PORTB_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A030_LABEL
+#define CONFIG_GPIO_GECKO_PORTC_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A060_LABEL
+#define CONFIG_GPIO_GECKO_PORTD_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A090_LABEL
+#define CONFIG_GPIO_GECKO_PORTE_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A0C0_LABEL
+#define CONFIG_GPIO_GECKO_PORTF_NAME	SILABS_EFR32XG1_GPIO_PORT_4000A0F0_LABEL
+
 /* End of SoC Level DTS fixup file */