drivers: eth: add driver for w5500 Ethernet Controller
Add driver for w5500 Ethernet Controller Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
This commit is contained in:
parent
5ead7e7b3b
commit
c2ee9f5c3e
10 changed files with 783 additions and 1 deletions
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@ -183,7 +183,8 @@
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/drivers/espi/ @albertofloyd @franciscomunoz @scottwcpg
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/drivers/espi/*npcx* @MulinChao
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/drivers/ethernet/ @jukkar @tbursztyka @pfalcon
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/drivers/ethernet/*stm32* @Nukersson @lochej
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/drivers/ethernet/*stm32* @Nukersson, @lochej
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/drivers/ethernet/*w5500* @parthitce
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/drivers/flash/ @nashif @nvlsianpu
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/drivers/flash/*nrf* @nvlsianpu
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/drivers/flash/*spi_nor* @pabigot
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@ -20,6 +20,7 @@ zephyr_sources_ifdef(CONFIG_ETH_MCUX eth_mcux.c)
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zephyr_sources_ifdef(CONFIG_ETH_SMSC911X eth_smsc911x.c)
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zephyr_sources_ifdef(CONFIG_ETH_STM32_HAL eth_stm32_hal.c)
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zephyr_sources_ifdef(CONFIG_ETH_LITEETH eth_liteeth.c)
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zephyr_sources_ifdef(CONFIG_ETH_W5500 eth_w5500.c)
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if(CONFIG_ETH_NATIVE_POSIX)
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zephyr_library()
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@ -55,5 +55,6 @@ source "drivers/ethernet/Kconfig.native_posix"
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source "drivers/ethernet/Kconfig.stellaris"
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source "drivers/ethernet/Kconfig.liteeth"
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source "drivers/ethernet/Kconfig.gecko"
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source "drivers/ethernet/Kconfig.w5500"
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endmenu # "Ethernet Drivers"
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37
drivers/ethernet/Kconfig.w5500
Normal file
37
drivers/ethernet/Kconfig.w5500
Normal file
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@ -0,0 +1,37 @@
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# W5500 Ethernet driver configuration options
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# Copyright (c) 2020 Linumiz
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# Author: Parthiban Nallathambi <parthiban@linumiz.com>
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# SPDX-License-Identifier: Apache-2.0
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menuconfig ETH_W5500
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bool "W5500 Ethernet Controller"
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depends on SPI
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help
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W5500 Stand-Alone Ethernet Controller
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with SPI Interface
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config ETH_W5500_RX_THREAD_STACK_SIZE
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int "Stack size for internal incoming packet handler"
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depends on ETH_W5500
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default 800
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help
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Size of the stack used for internal thread which is ran for
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incoming packet processing.
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config ETH_W5500_RX_THREAD_PRIO
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int "Priority for internal incoming packet handler"
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depends on ETH_W5500
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default 2
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help
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Priority level for internal thread which is ran for incoming
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packet processing.
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config ETH_W5500_TIMEOUT
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int "IP buffer timeout"
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depends on ETH_W5500
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default 100
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help
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Given timeout in milliseconds. Maximum amount of time
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that the driver will wait from the IP stack to get
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a memory buffer before the Ethernet frame is dropped.
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591
drivers/ethernet/eth_w5500.c
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591
drivers/ethernet/eth_w5500.c
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@ -0,0 +1,591 @@
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/* W5500 Stand-alone Ethernet Controller with SPI
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*
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* Copyright (c) 2020 Linumiz
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* Author: Parthiban Nallathambi <parthiban@linumiz.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT wiznet_w5500
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#include <logging/log.h>
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LOG_MODULE_REGISTER(eth_w5500, CONFIG_ETHERNET_LOG_LEVEL);
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#include <zephyr.h>
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#include <device.h>
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#include <string.h>
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#include <errno.h>
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#include <drivers/gpio.h>
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#include <drivers/spi.h>
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#include <net/net_pkt.h>
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#include <net/net_if.h>
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#include <net/ethernet.h>
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#include <ethernet/eth_stats.h>
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#include "eth.h"
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#include "eth_w5500_priv.h"
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#define WIZNET_OUI_B0 0x00
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#define WIZNET_OUI_B1 0x08
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#define WIZNET_OUI_B2 0xdc
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#define W5500_SPI_BLOCK_SELECT(addr) (((addr) >> 16) & 0x1f)
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#define W5500_SPI_READ_CONTROL(addr) (W5500_SPI_BLOCK_SELECT(addr) << 3)
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#define W5500_SPI_WRITE_CONTROL(addr) \
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((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2))
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static int w5500_spi_read(const struct device *dev, uint32_t addr,
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uint8_t *data, uint32_t len)
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{
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int ret;
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struct w5500_runtime *ctx = dev->data;
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/* 3 bytes as 0x010203 during command phase */
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uint8_t tmp[len + 3];
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uint8_t cmd[3] = {
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addr >> 8,
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addr,
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W5500_SPI_READ_CONTROL(addr)
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};
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const struct spi_buf tx_buf = {
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.buf = cmd,
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.len = ARRAY_SIZE(cmd),
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};
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const struct spi_buf_set tx = {
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.buffers = &tx_buf,
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.count = 1,
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};
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const struct spi_buf rx_buf = {
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.buf = tmp,
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.len = ARRAY_SIZE(tmp),
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};
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const struct spi_buf_set rx = {
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.buffers = &rx_buf,
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.count = 1,
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};
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ret = spi_transceive(ctx->spi, &ctx->spi_cfg, &tx, &rx);
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if (!ret) {
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/* skip the default dummy 0x010203 */
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memcpy(data, &tmp[3], len);
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}
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return ret;
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}
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static int w5500_spi_write(const struct device *dev, uint32_t addr,
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uint8_t *data, uint32_t len)
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{
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int ret;
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struct w5500_runtime *ctx = dev->data;
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uint8_t cmd[3] = {
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addr >> 8,
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addr,
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W5500_SPI_WRITE_CONTROL(addr),
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};
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const struct spi_buf tx_buf[2] = {
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{
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.buf = cmd,
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.len = ARRAY_SIZE(cmd),
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},
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{
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.buf = data,
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.len = len,
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},
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};
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const struct spi_buf_set tx = {
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.buffers = tx_buf,
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.count = ARRAY_SIZE(tx_buf),
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};
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ret = spi_write(ctx->spi, &ctx->spi_cfg, &tx);
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return ret;
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}
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static int w5500_readbuf(const struct device *dev, uint16_t offset, uint8_t *buf,
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int len)
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{
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uint32_t addr;
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int remain = 0;
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int ret;
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const uint32_t mem_start = W5500_Sn_RX_MEM_START;
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const uint16_t mem_size = W5500_RX_MEM_SIZE;
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offset %= mem_size;
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addr = mem_start + offset;
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if (offset + len > mem_size) {
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remain = (offset + len) % mem_size;
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len = mem_size - offset;
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}
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ret = w5500_spi_read(dev, addr, buf, len);
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if (ret || !remain) {
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return ret;
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}
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return w5500_spi_read(dev, mem_start, buf + len, remain);
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}
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static int w5500_writebuf(const struct device *dev, uint16_t offset, uint8_t *buf,
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int len)
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{
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uint32_t addr;
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int ret = 0;
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int remain = 0;
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const uint32_t mem_start = W5500_Sn_TX_MEM_START;
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const uint32_t mem_size = W5500_TX_MEM_SIZE;
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offset %= mem_size;
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addr = mem_start + offset;
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if (offset + len > mem_size) {
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remain = (offset + len) % mem_size;
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len = mem_size - offset;
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}
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ret = w5500_spi_write(dev, addr, buf, len);
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if (ret || !remain) {
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return ret;
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}
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return w5500_spi_write(dev, mem_start, buf + len, remain);
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}
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static int w5500_command(const struct device *dev, uint8_t cmd)
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{
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uint8_t reg;
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uint64_t end = z_timeout_end_calc(K_MSEC(100));
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w5500_spi_write(dev, W5500_S0_CR, &cmd, 1);
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do {
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w5500_spi_read(dev, W5500_S0_CR, ®, 1);
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if (end - z_tick_get() <= 0) {
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return -EIO;
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}
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k_msleep(1);
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} while (reg != 0);
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return 0;
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}
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static int w5500_tx(const struct device *dev, struct net_pkt *pkt)
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{
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struct w5500_runtime *ctx = dev->data;
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uint16_t len = net_pkt_get_len(pkt);
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uint16_t offset;
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uint8_t off[2];
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int ret;
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w5500_spi_read(dev, W5500_S0_TX_WR, off, 2);
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offset = sys_get_be16(off);
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if (net_pkt_read(pkt, ctx->buf, len)) {
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return -EIO;
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}
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ret = w5500_writebuf(dev, offset, ctx->buf, len);
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if (ret < 0) {
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return ret;
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}
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sys_put_be16(offset + len, off);
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w5500_spi_write(dev, W5500_S0_TX_WR, off, 2);
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w5500_command(dev, S0_CR_SEND);
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if (k_sem_take(&ctx->tx_sem, K_MSEC(10))) {
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return -EIO;
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}
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return 0;
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}
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static void w5500_rx(const struct device *dev)
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{
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uint8_t mask = 0;
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uint8_t header[2];
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uint8_t tmp[2];
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uint16_t off;
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uint16_t rx_len;
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uint16_t rx_buf_len;
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uint16_t read_len;
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uint16_t reader;
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struct net_buf *pkt_buf = NULL;
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struct net_pkt *pkt;
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struct w5500_runtime *ctx = dev->data;
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const struct w5500_config *config = dev->config;
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/* disable interrupt */
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w5500_spi_write(dev, W5500_SIMR, &mask, 1);
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w5500_spi_read(dev, W5500_S0_RX_RSR, tmp, 2);
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rx_buf_len = sys_get_be16(tmp);
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if (rx_buf_len == 0) {
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return;
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}
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w5500_spi_read(dev, W5500_S0_RX_RD, tmp, 2);
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off = sys_get_be16(tmp);
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w5500_readbuf(dev, off, header, 2);
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rx_len = sys_get_be16(header) - 2;
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pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, rx_len,
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AF_UNSPEC, 0, K_MSEC(config->timeout));
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if (!pkt) {
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eth_stats_update_errors_rx(ctx->iface);
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return;
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}
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pkt_buf = pkt->buffer;
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read_len = rx_len;
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reader = off + 2;
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do {
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size_t frag_len;
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uint8_t *data_ptr;
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size_t frame_len;
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data_ptr = pkt_buf->data;
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frag_len = net_buf_tailroom(pkt_buf);
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if (read_len > frag_len) {
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frame_len = frag_len;
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} else {
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frame_len = read_len;
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}
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w5500_readbuf(dev, reader, data_ptr, frame_len);
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net_buf_add(pkt_buf, frame_len);
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reader += frame_len;
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read_len -= frame_len;
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pkt_buf = pkt_buf->frags;
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} while (read_len > 0);
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if (net_recv_data(ctx->iface, pkt) < 0) {
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net_pkt_unref(pkt);
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}
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sys_put_be16(off + 2 + rx_len, tmp);
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w5500_spi_write(dev, W5500_S0_RX_RD, tmp, 2);
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w5500_command(dev, S0_CR_RECV);
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}
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static void w5500_isr(const struct device *dev)
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{
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uint8_t ir;
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uint8_t mask = 0;
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struct w5500_runtime *ctx = dev->data;
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while (true) {
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k_sem_take(&ctx->int_sem, K_FOREVER);
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w5500_spi_read(dev, W5500_S0_IR, &ir, 1);
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if (!ir) {
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goto done;
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}
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w5500_spi_write(dev, W5500_S0_IR, &ir, 1);
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if (ir & S0_IR_SENDOK) {
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k_sem_give(&ctx->tx_sem);
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LOG_DBG("TX Done");
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}
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if (ir & S0_IR_RECV) {
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w5500_rx(dev);
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}
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done:
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/* enable interrupt */
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mask = IR_S0;
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w5500_spi_write(dev, W5500_SIMR, &mask, 1);
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}
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}
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static void w5500_iface_init(struct net_if *iface)
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{
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const struct device *dev = net_if_get_device(iface);
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struct w5500_runtime *ctx = dev->data;
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net_if_set_link_addr(iface, ctx->mac_addr,
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sizeof(ctx->mac_addr),
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NET_LINK_ETHERNET);
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if (!ctx->iface) {
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ctx->iface = iface;
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}
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ethernet_init(iface);
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}
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static enum ethernet_hw_caps w5500_get_capabilities(const struct device *dev)
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{
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ARG_UNUSED(dev);
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return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T
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#if defined(CONFIG_NET_PROMISCUOUS_MODE)
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| ETHERNET_PROMISC_MODE
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#endif
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;
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}
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static int w5500_set_config(const struct device *dev,
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enum ethernet_config_type type,
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const struct ethernet_config *config)
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{
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uint8_t mode;
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uint8_t mr = W5500_S0_MR_MF;
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w5500_spi_read(dev, W5500_S0_MR, &mode, 1);
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if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE) &&
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type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
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if (config->promisc_mode) {
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if (!(mode & W5500_S0_MR_MF))
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return -EALREADY;
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}
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/* clear */
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WRITE_BIT(mode, mr, 0);
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} else {
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if (mode & mr) {
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return -EALREADY;
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}
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/* set */
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WRITE_BIT(mode, mr, 1);
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}
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return w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
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}
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static int w5500_hw_start(const struct device *dev)
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{
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uint8_t mode = S0_MR_MACRAW;
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uint8_t mask = IR_S0;
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w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
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w5500_command(dev, S0_CR_OPEN);
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/* enable interrupt */
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w5500_spi_write(dev, W5500_SIMR, &mask, 1);
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return 0;
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}
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static int w5500_hw_stop(const struct device *dev)
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{
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uint8_t mask = 0;
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/* disable interrupt */
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w5500_spi_write(dev, W5500_SIMR, &mask, 1);
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w5500_command(dev, S0_CR_CLOSE);
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return 0;
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}
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static struct ethernet_api w5500_api_funcs = {
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.iface_api.init = w5500_iface_init,
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.get_capabilities = w5500_get_capabilities,
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.set_config = w5500_set_config,
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.start = w5500_hw_start,
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.stop = w5500_hw_stop,
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.send = w5500_tx,
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};
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static int w5500_hw_reset(const struct device *dev)
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{
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int ret;
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uint8_t mask = 0;
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uint8_t tmp = MR_RST;
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ret = w5500_spi_write(dev, W5500_MR, &tmp, 1);
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if (ret < 0) {
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return ret;
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}
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k_msleep(5);
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tmp = MR_PB;
|
||||
w5500_spi_write(dev, W5500_MR, &tmp, 1);
|
||||
|
||||
/* disable interrupt */
|
||||
return w5500_spi_write(dev, W5500_SIMR, &mask, 1);
|
||||
}
|
||||
|
||||
static void w5500_gpio_callback(const struct device *dev,
|
||||
struct gpio_callback *cb,
|
||||
uint32_t pins)
|
||||
{
|
||||
struct w5500_runtime *ctx =
|
||||
CONTAINER_OF(cb, struct w5500_runtime, gpio_cb);
|
||||
|
||||
k_sem_give(&ctx->int_sem);
|
||||
}
|
||||
|
||||
static void w5500_set_macaddr(const struct device *dev)
|
||||
{
|
||||
struct w5500_runtime *ctx = dev->data;
|
||||
|
||||
/* override vendor bytes */
|
||||
memset(ctx->mac_addr, '\0', sizeof(ctx->mac_addr));
|
||||
ctx->mac_addr[0] = WIZNET_OUI_B0;
|
||||
ctx->mac_addr[1] = WIZNET_OUI_B1;
|
||||
ctx->mac_addr[2] = WIZNET_OUI_B2;
|
||||
if (ctx->generate_mac) {
|
||||
ctx->generate_mac(ctx->mac_addr);
|
||||
}
|
||||
|
||||
w5500_spi_write(dev, W5500_SHAR, ctx->mac_addr, sizeof(ctx->mac_addr));
|
||||
}
|
||||
|
||||
static void w5500_memory_configure(const struct device *dev)
|
||||
{
|
||||
int i;
|
||||
uint8_t mem = 0x10;
|
||||
|
||||
/* Configure RX & TX memory to 16K */
|
||||
w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(0), &mem, 1);
|
||||
w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(0), &mem, 1);
|
||||
|
||||
mem = 0;
|
||||
for (i = 1; i < 8; i++) {
|
||||
w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(i), &mem, 1);
|
||||
w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(i), &mem, 1);
|
||||
}
|
||||
}
|
||||
|
||||
static void w5500_random_mac(uint8_t *mac_addr)
|
||||
{
|
||||
gen_random_mac(mac_addr, WIZNET_OUI_B0, WIZNET_OUI_B1, WIZNET_OUI_B2);
|
||||
}
|
||||
|
||||
static int w5500_init(const struct device *dev)
|
||||
{
|
||||
int err;
|
||||
uint8_t rtr[2];
|
||||
const struct w5500_config *config = dev->config;
|
||||
struct w5500_runtime *ctx = dev->data;
|
||||
|
||||
ctx->spi_cfg.operation = SPI_WORD_SET(8);
|
||||
ctx->spi_cfg.frequency = config->spi_freq;
|
||||
ctx->spi_cfg.slave = config->spi_slave;
|
||||
|
||||
ctx->spi = device_get_binding((char *)config->spi_port);
|
||||
if (!ctx->spi) {
|
||||
LOG_ERR("SPI master port %s not found", config->spi_port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
|
||||
ctx->spi_cs.gpio_dev = device_get_binding((char *)config->spi_cs_port);
|
||||
if (!ctx->spi_cs.gpio_dev) {
|
||||
LOG_ERR("SPI CS port %s not found", config->spi_cs_port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ctx->spi_cs.gpio_pin = config->spi_cs_pin;
|
||||
ctx->spi_cs.gpio_dt_flags = config->spi_cs_dt_flags;
|
||||
ctx->spi_cfg.cs = &ctx->spi_cs;
|
||||
#endif
|
||||
|
||||
ctx->gpio = device_get_binding((char *)config->gpio_port);
|
||||
if (!ctx->gpio) {
|
||||
LOG_ERR("GPIO port %s not found", config->gpio_port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (gpio_pin_configure(ctx->gpio, config->gpio_pin,
|
||||
GPIO_INPUT | config->gpio_flags)) {
|
||||
LOG_ERR("Unable to configure GPIO pin %u", config->gpio_pin);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpio_init_callback(&(ctx->gpio_cb), w5500_gpio_callback,
|
||||
BIT(config->gpio_pin));
|
||||
|
||||
if (gpio_add_callback(ctx->gpio, &(ctx->gpio_cb))) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpio_pin_interrupt_configure(ctx->gpio,
|
||||
config->gpio_pin,
|
||||
GPIO_INT_EDGE_FALLING);
|
||||
|
||||
ctx->reset = device_get_binding((char *)config->reset_port);
|
||||
if (!ctx->reset) {
|
||||
LOG_ERR("GPIO port %s not found", config->reset_port);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (gpio_pin_configure(ctx->reset, config->reset_pin,
|
||||
GPIO_OUTPUT | config->reset_flags)) {
|
||||
LOG_ERR("Unable to configure GPIO pin %u", config->reset_pin);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
gpio_pin_set(ctx->reset, DT_INST_GPIO_PIN(0, reset_gpios), 0);
|
||||
k_usleep(500);
|
||||
|
||||
err = w5500_hw_reset(dev);
|
||||
if (err) {
|
||||
LOG_ERR("Reset failed");
|
||||
return err;
|
||||
}
|
||||
|
||||
w5500_set_macaddr(dev);
|
||||
w5500_memory_configure(dev);
|
||||
|
||||
/* check retry time value */
|
||||
w5500_spi_read(dev, W5500_RTR, rtr, 2);
|
||||
if (sys_get_be16(rtr) != RTR_DEFAULT) {
|
||||
LOG_ERR("Unable to read RTR register");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
k_thread_create(&ctx->thread, ctx->thread_stack,
|
||||
CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE,
|
||||
(k_thread_entry_t)w5500_isr,
|
||||
(void *)dev, NULL, NULL,
|
||||
K_PRIO_COOP(CONFIG_ETH_W5500_RX_THREAD_PRIO),
|
||||
0, K_NO_WAIT);
|
||||
|
||||
LOG_INF("W5500 Initialized");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct w5500_runtime w5500_0_runtime = {
|
||||
.generate_mac = w5500_random_mac,
|
||||
.tx_sem = Z_SEM_INITIALIZER(w5500_0_runtime.tx_sem,
|
||||
1, UINT_MAX),
|
||||
.int_sem = Z_SEM_INITIALIZER(w5500_0_runtime.int_sem,
|
||||
0, UINT_MAX),
|
||||
};
|
||||
|
||||
static const struct w5500_config w5500_0_config = {
|
||||
.gpio_port = DT_INST_GPIO_LABEL(0, int_gpios),
|
||||
.gpio_pin = DT_INST_GPIO_PIN(0, int_gpios),
|
||||
.gpio_flags = DT_INST_GPIO_FLAGS(0, int_gpios),
|
||||
.reset_port = DT_INST_GPIO_LABEL(0, reset_gpios),
|
||||
.reset_pin = DT_INST_GPIO_PIN(0, reset_gpios),
|
||||
.reset_flags = DT_INST_GPIO_FLAGS(0, reset_gpios),
|
||||
.spi_port = DT_INST_BUS_LABEL(0),
|
||||
.spi_freq = DT_INST_PROP(0, spi_max_frequency),
|
||||
.spi_slave = DT_INST_REG_ADDR(0),
|
||||
#if DT_INST_SPI_DEV_HAS_CS_GPIOS(0)
|
||||
.spi_cs_port = DT_INST_SPI_DEV_CS_GPIOS_LABEL(0),
|
||||
.spi_cs_pin = DT_INST_SPI_DEV_CS_GPIOS_PIN(0),
|
||||
.spi_cs_dt_flags = DT_INST_SPI_DEV_CS_GPIOS_FLAGS(0),
|
||||
#endif
|
||||
.timeout = CONFIG_ETH_W5500_TIMEOUT,
|
||||
};
|
||||
|
||||
ETH_NET_DEVICE_INIT(eth_w5500, DT_INST_LABEL(0),
|
||||
w5500_init, device_pm_control_nop,
|
||||
&w5500_0_runtime, &w5500_0_config,
|
||||
CONFIG_ETH_INIT_PRIORITY, &w5500_api_funcs, NET_ETH_MTU);
|
113
drivers/ethernet/eth_w5500_priv.h
Normal file
113
drivers/ethernet/eth_w5500_priv.h
Normal file
|
@ -0,0 +1,113 @@
|
|||
/* W5500 Stand-alone Ethernet Controller with SPI
|
||||
*
|
||||
* Copyright (c) 2020 Linumiz
|
||||
* Author: Parthiban Nallathambi <parthiban@linumiz.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _W5500_
|
||||
#define _W5500_
|
||||
|
||||
/*
|
||||
* W5500 common registers
|
||||
*/
|
||||
#define W5500_COMMON_REGS 0x0000
|
||||
#define W5500_MR 0x0000 /* Mode Register */
|
||||
#define W5500_GW 0x0001
|
||||
#define MR_RST 0x80 /* S/W reset */
|
||||
#define MR_PB 0x10 /* Ping block */
|
||||
#define MR_AI 0x02 /* Address Auto-Increment */
|
||||
#define MR_IND 0x01 /* Indirect mode */
|
||||
#define W5500_SHAR 0x0009 /* Source MAC address */
|
||||
#define W5500_IR 0x0015 /* Interrupt Register */
|
||||
#define W5500_COMMON_REGS_LEN 0x0040
|
||||
|
||||
#define W5500_Sn_MR 0x0000 /* Sn Mode Register */
|
||||
#define W5500_Sn_CR 0x0001 /* Sn Command Register */
|
||||
#define W5500_Sn_IR 0x0002 /* Sn Interrupt Register */
|
||||
#define W5500_Sn_SR 0x0003 /* Sn Status Register */
|
||||
#define W5500_Sn_TX_FSR 0x0020 /* Sn Transmit free memory size */
|
||||
#define W5500_Sn_TX_RD 0x0022 /* Sn Transmit memory read pointer */
|
||||
#define W5500_Sn_TX_WR 0x0024 /* Sn Transmit memory write pointer */
|
||||
#define W5500_Sn_RX_RSR 0x0026 /* Sn Receive free memory size */
|
||||
#define W5500_Sn_RX_RD 0x0028 /* Sn Receive memory read pointer */
|
||||
|
||||
#define W5500_S0_REGS 0x10000
|
||||
|
||||
#define W5500_S0_MR (W5500_S0_REGS + W5500_Sn_MR)
|
||||
#define S0_MR_MACRAW 0x04 /* MAC RAW mode */
|
||||
#define S0_MR_MF 0x40 /* MAC Filter for W5500 */
|
||||
#define W5500_S0_CR (W5500_S0_REGS + W5500_Sn_CR)
|
||||
#define S0_CR_OPEN 0x01 /* OPEN command */
|
||||
#define S0_CR_CLOSE 0x10 /* CLOSE command */
|
||||
#define S0_CR_SEND 0x20 /* SEND command */
|
||||
#define S0_CR_RECV 0x40 /* RECV command */
|
||||
#define W5500_S0_IR (W5500_S0_REGS + W5500_Sn_IR)
|
||||
#define S0_IR_SENDOK 0x10 /* complete sending */
|
||||
#define S0_IR_RECV 0x04 /* receiving data */
|
||||
#define W5500_S0_SR (W5500_S0_REGS + W5500_Sn_SR)
|
||||
#define S0_SR_MACRAW 0x42 /* mac raw mode */
|
||||
#define W5500_S0_TX_FSR (W5500_S0_REGS + W5500_Sn_TX_FSR)
|
||||
#define W5500_S0_TX_RD (W5500_S0_REGS + W5500_Sn_TX_RD)
|
||||
#define W5500_S0_TX_WR (W5500_S0_REGS + W5500_Sn_TX_WR)
|
||||
#define W5500_S0_RX_RSR (W5500_S0_REGS + W5500_Sn_RX_RSR)
|
||||
#define W5500_S0_RX_RD (W5500_S0_REGS + W5500_Sn_RX_RD)
|
||||
#define W5500_S0_IMR (W5500_S0_REGS + W5500_Sn_IMR)
|
||||
|
||||
#define W5500_S0_MR_MF BIT(7) /* MAC Filter for W5500 */
|
||||
#define W5500_Sn_REGS_LEN 0x0040
|
||||
#define W5500_SIMR 0x0018 /* Socket Interrupt Mask Register */
|
||||
#define IR_S0 0x01
|
||||
#define RTR_DEFAULT 2000
|
||||
#define W5500_RTR 0x0019 /* Retry Time-value Register */
|
||||
|
||||
|
||||
#define W5500_Sn_RXMEM_SIZE(n) \
|
||||
(0x1001e + (n) * 0x40000) /* Sn RX Memory Size */
|
||||
#define W5500_Sn_TXMEM_SIZE(n) \
|
||||
(0x1001f + (n) * 0x40000) /* Sn TX Memory Size */
|
||||
|
||||
#define W5500_Sn_TX_MEM_START 0x20000
|
||||
#define W5500_TX_MEM_SIZE 0x04000
|
||||
#define W5500_Sn_RX_MEM_START 0x30000
|
||||
#define W5500_RX_MEM_SIZE 0x04000
|
||||
|
||||
struct w5500_config {
|
||||
void (*config_func)(void);
|
||||
const char *gpio_port;
|
||||
uint8_t gpio_pin;
|
||||
gpio_dt_flags_t gpio_flags;
|
||||
const char *reset_port;
|
||||
uint8_t reset_pin;
|
||||
gpio_dt_flags_t reset_flags;
|
||||
const char *spi_port;
|
||||
gpio_pin_t spi_cs_pin;
|
||||
gpio_dt_flags_t spi_cs_dt_flags;
|
||||
const char *spi_cs_port;
|
||||
uint32_t spi_freq;
|
||||
uint8_t spi_slave;
|
||||
uint8_t full_duplex;
|
||||
int32_t timeout;
|
||||
};
|
||||
|
||||
struct w5500_runtime {
|
||||
struct net_if *iface;
|
||||
|
||||
K_THREAD_STACK_MEMBER(thread_stack,
|
||||
CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE);
|
||||
struct k_thread thread;
|
||||
uint8_t mac_addr[6];
|
||||
const struct device *gpio;
|
||||
const struct device *reset;
|
||||
const struct device *spi;
|
||||
struct spi_cs_control spi_cs;
|
||||
struct spi_config spi_cfg;
|
||||
struct gpio_callback gpio_cb;
|
||||
struct k_sem tx_sem;
|
||||
struct k_sem int_sem;
|
||||
void (*generate_mac)(uint8_t *mac);
|
||||
uint8_t buf[NET_ETH_MAX_FRAME_SIZE];
|
||||
};
|
||||
|
||||
#endif /*_W5500_*/
|
26
dts/bindings/ethernet/wiznet,w5500.yaml
Normal file
26
dts/bindings/ethernet/wiznet,w5500.yaml
Normal file
|
@ -0,0 +1,26 @@
|
|||
# Copyright (c) 2020 Linumiz
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: W5500 standalone 10/100BASE-T Ethernet controller with SPI interface
|
||||
|
||||
compatible: "wiznet,w5500"
|
||||
|
||||
include: [spi-device.yaml, ethernet.yaml]
|
||||
|
||||
properties:
|
||||
int-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: Interrupt pin.
|
||||
|
||||
The interrupt pin of W5500 is active low.
|
||||
If connected directly the MCU pin should be configured
|
||||
as active low.
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: Reset pin.
|
||||
|
||||
The reset pin of W5500 is active low.
|
||||
If connected directly the MCU pin should be configured
|
||||
as active low.
|
|
@ -101,6 +101,7 @@
|
|||
<&test_gpio 0 0>,
|
||||
<&test_gpio 0 0>,
|
||||
<&test_gpio 0 0>,
|
||||
<&test_gpio 0 0>,
|
||||
<&test_gpio 0 0>;
|
||||
|
||||
#include "spi.dtsi"
|
||||
|
|
|
@ -11,3 +11,5 @@ CONFIG_TEST_USERSPACE=y
|
|||
CONFIG_SPI=y
|
||||
CONFIG_ETH_ENC28J60=y
|
||||
CONFIG_ETH_ENC28J60_0=y
|
||||
|
||||
CONFIG_ETH_W5500=y
|
||||
|
|
|
@ -542,3 +542,12 @@ test_spi_dac80508: dac80508@35 {
|
|||
channel6-gain = <0>;
|
||||
channel7-gain = <0>;
|
||||
};
|
||||
|
||||
test_spi_w5500: w5500@36 {
|
||||
compatible = "wiznet,w5500";
|
||||
label = "w5500";
|
||||
reg = <0x36>;
|
||||
spi-max-frequency = <0>;
|
||||
int-gpios = <&test_gpio 0 0>;
|
||||
reset-gpios = <&test_gpio 0 0>;
|
||||
};
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue