From c2842c388d8eaf20e17fc90de4d81005a4bcc20d Mon Sep 17 00:00:00 2001 From: Torsten Rasmussen Date: Thu, 10 Jun 2021 15:38:20 +0200 Subject: [PATCH] cmake: linker: arm: adding Zephyr CMake linker files for arm arch This is the initial version of a Zephyr CMake linker file for the arm architecture. This file defines memory regions, groups, linker sections and symbols for the arm architecture. It also sources the common common-ram.cmake, common-rom.cmake, debug-sections,cmake, and thread-local-storage.cmake. It configure sections for SoC families using zephyr_linker_sources() functions: - nxp_imx Signed-off-by: Torsten Rasmussen --- CMakeLists.txt | 2 + cmake/linker_script/arm/linker.cmake | 169 +++++++++++++++++++++++++++ soc/arm/nxp_imx/rt/CMakeLists.txt | 22 ++++ 3 files changed, 193 insertions(+) create mode 100644 cmake/linker_script/arm/linker.cmake diff --git a/CMakeLists.txt b/CMakeLists.txt index 4a41792546d..ea473b688c1 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -77,6 +77,8 @@ zephyr_include_directories( ${STDINCLUDE} ) +include(${ZEPHYR_BASE}/cmake/linker_script/${ARCH}/linker.cmake OPTIONAL) + # Don't add non-existing include directories, it creates noise and # warnings in some tooling foreach(optional_include_dir diff --git a/cmake/linker_script/arm/linker.cmake b/cmake/linker_script/arm/linker.cmake new file mode 100644 index 00000000000..a98cb7b3060 --- /dev/null +++ b/cmake/linker_script/arm/linker.cmake @@ -0,0 +1,169 @@ +set(COMMON_ZEPHYR_LINKER_DIR ${ZEPHYR_BASE}/cmake/linker_script/common) + +set_ifndef(region_min_align CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE) + +# Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE if not set above +# to make linker section alignment comply with MPU granularity. +set_ifndef(region_min_align CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE) + +# If building without MPU support, use default 4-byte alignment.. if not set abve. +set_ifndef(region_min_align 4) + +# Note, the `+ 0` in formulas below avoids errors in cases where a Kconfig +# variable is undefined and thus expands to nothing. +math(EXPR FLASH_ADDR + "${CONFIG_FLASH_BASE_ADDRESS} + ${CONFIG_FLASH_LOAD_OFFSET} + 0" + OUTPUT_FORMAT HEXADECIMAL +) + +math(EXPR FLASH_SIZE + "(${CONFIG_FLASH_SIZE} + 0) * 1024 - (${CONFIG_FLASH_LOAD_OFFSET} + 0)" + OUTPUT_FORMAT HEXADECIMAL +) + +set(RAM_ADDR ${CONFIG_SRAM_BASE_ADDRESS}) +math(EXPR RAM_SIZE "(${CONFIG_SRAM_SIZE} + 0) * 1024" OUTPUT_FORMAT HEXADECIMAL) +math(EXPR IDT_ADDR "${RAM_ADDR} + ${RAM_SIZE}" OUTPUT_FORMAT HEXADECIMAL) + +# ToDo: decide on the optimal location for this. +# linker/ld/target.cmake based on arch, or directly in arch and scatter_script.cmake can ignore +zephyr_linker(FORMAT "elf32-littlearm") +zephyr_linker(ENTRY ${CONFIG_KERNEL_ENTRY}) + +zephyr_linker_memory(NAME FLASH FLAGS rx START ${FLASH_ADDR} SIZE ${FLASH_SIZE}) +zephyr_linker_memory(NAME RAM FLAGS wx START ${RAM_ADDR} SIZE ${RAM_SIZE}) +zephyr_linker_memory(NAME IDT_LIST FLAGS wx START ${IDT_ADDR} SIZE 2K) + +if(CONFIG_XIP) + zephyr_linker_group(NAME ROM_REGION LMA FLASH) + set(rom_start ${FLASH_ADDR}) + set(XIP_ALIGN_WITH_INPUT ALIGN_WITH_INPUT) +else() + zephyr_linker_group(NAME ROM_REGION LMA RAM) + set(rom_start ${RAM_ADDR}) +endif() + +zephyr_linker_group(NAME RAM_REGION VMA RAM LMA ROM_REGION) +zephyr_linker_group(NAME TEXT_REGION GROUP ROM_REGION) +zephyr_linker_group(NAME RODATA_REGION GROUP ROM_REGION) +zephyr_linker_group(NAME DATA_REGION GROUP RAM_REGION) + +# should go to a relocation.cmake - from include/linker/rel-sections.ld - start +zephyr_linker_section(NAME .rel.plt HIDDEN) +zephyr_linker_section(NAME .rela.plt HIDDEN) +zephyr_linker_section(NAME .rel.dyn) +zephyr_linker_section(NAME .rela.dyn) +# should go to a relocation.cmake - from include/linker/rel-sections.ld - end + +# Discard sections for GNU ld. +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".plt") +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".iplt") +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".got.plt") +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".igot.plt") +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".got") +zephyr_linker_section_configure(SECTION /DISCARD/ INPUT ".igot") + +zephyr_linker_section(NAME .rom_start ADDRESS ${rom_start} GROUP ROM_REGION NOINPUT) + +zephyr_linker_section(NAME .text GROUP TEXT_REGION) + +zephyr_linker_section_configure(SECTION .rel.plt INPUT ".rel.iplt") +zephyr_linker_section_configure(SECTION .rela.plt INPUT ".rela.iplt") + +zephyr_linker_section_configure(SECTION .text INPUT ".TEXT.*") +zephyr_linker_section_configure(SECTION .text INPUT ".gnu.linkonce.t.*") + +zephyr_linker_section_configure(SECTION .text INPUT ".glue_7t") +zephyr_linker_section_configure(SECTION .text INPUT ".glue_7") +zephyr_linker_section_configure(SECTION .text INPUT ".vfp11_veneer") +zephyr_linker_section_configure(SECTION .text INPUT ".v4_bx") + +if(CONFIG_CPLUSPLUS) + zephyr_linker_section(NAME .ARM.extab GROUP ROM_REGION) + zephyr_linker_section_configure(SECTION .ARM.extab INPUT ".gnu.linkonce.armextab.*") +endif() + +zephyr_linker_section(NAME .ARM.exidx GROUP ROM_REGION) +# Here the original linker would check for __GCC_LINKER_CMD__, need to check toolchain linker ? +#if(__GCC_LINKER_CMD__) + zephyr_linker_section_configure(SECTION .ARM.exidx INPUT ".gnu.linkonce.armexidx.*") +#endif() + + +include(${COMMON_ZEPHYR_LINKER_DIR}/common-rom.cmake) +include(${COMMON_ZEPHYR_LINKER_DIR}/thread-local-storage.cmake) + +zephyr_linker_section(NAME .rodata GROUP RODATA_REGION) +zephyr_linker_section_configure(SECTION .rodata INPUT ".gnu.linkonce.r.*") +if(CONFIG_USERSPACE AND CONFIG_XIP) + zephyr_linker_section_configure(SECTION .rodata INPUT ".kobject_data.rodata*") +endif() +zephyr_linker_section_configure(SECTION .rodata ALIGN 4) + +# ToDo - . = ALIGN(_region_min_align); +# Symbol to add _image_ram_start = .; + +# This comes from ramfunc.ls, via snippets-ram-sections.ld +zephyr_linker_section(NAME .ramfunc GROUP RAM_REGION SUBALIGN 8) +# Todo: handle MPU_ALIGN(_ramfunc_size); + +# ToDo - handle if(CONFIG_USERSPACE) + +zephyr_linker_section(NAME .data GROUP DATA_REGION) +zephyr_linker_section_configure(SECTION .data INPUT ".kernel.*") + +include(${COMMON_ZEPHYR_LINKER_DIR}/common-ram.cmake) +#include(kobject.ld) + +if(NOT CONFIG_USERSPACE) + zephyr_linker_section(NAME .bss VMA RAM LMA FLASH TYPE BSS) + zephyr_linker_section_configure(SECTION .bss INPUT COMMON) + zephyr_linker_section_configure(SECTION .bss INPUT ".kernel_bss.*") + # As memory is cleared in words only, it is simpler to ensure the BSS + # section ends on a 4 byte boundary. This wastes a maximum of 3 bytes. + zephyr_linker_section_configure(SECTION .bss ALIGN 4) + + zephyr_linker_section(NAME .noinit GROUP RAM_REGION TYPE NOLOAD NOINIT) + # This section is used for non-initialized objects that + # will not be cleared during the boot process. + zephyr_linker_section_configure(SECTION .noinit INPUT ".kernel_noinit.*") +endif() + +zephyr_linker_symbol(SYMBOL __kernel_ram_start EXPR "(%__bss_start%)") +zephyr_linker_symbol(SYMBOL __kernel_ram_end EXPR "(${RAM_ADDR} + ${RAM_SIZE})") +zephyr_linker_symbol(SYMBOL __kernel_ram_size EXPR "(%__kernel_ram_end% - %__bss_start%)") +zephyr_linker_symbol(SYMBOL _image_ram_start EXPR "(${RAM_ADDR})" SUBALIGN 32) # ToDo calculate 32 correctly +zephyr_linker_symbol(SYMBOL ARM_LIB_STACKHEAP EXPR "(${RAM_ADDR} + ${RAM_SIZE})" SIZE -0x1000) + +set(VECTOR_ALIGN 4) +if(CONFIG_CPU_CORTEX_M_HAS_VTOR) + math(EXPR VECTOR_ALIGN "4 * (16 + ${CONFIG_NUM_IRQS})") + if(${VECTOR_ALIGN} LESS 128) + set(VECTOR_ALIGN 128) + else() + pow2round(VECTOR_ALIGN) + endif() +endif() + +zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".exc_vector_table*" + ".gnu.linkonce.irq_vector_table*" + ".vectors" + OFFSET ${CONFIG_ROM_START_OFFSET} + KEEP FIRST + SYMBOLS _vector_start _vector_end + ALIGN ${VECTOR_ALIGN} + PRIO 50 +) + +zephyr_linker_section(NAME .ARM.attributes ADDRESS 0 NOINPUT) +zephyr_linker_section_configure(SECTION .ARM.attributes INPUT ".ARM.attributes" KEEP) +zephyr_linker_section_configure(SECTION .ARM.attributes INPUT ".gnu.attributes" KEEP) + +# armlink specific flags +zephyr_linker_section_configure(SECTION .text ANY FLAGS "+RO" "+XO") +zephyr_linker_section_configure(SECTION .data ANY FLAGS "+RW") +zephyr_linker_section_configure(SECTION .bss ANY FLAGS "+ZI") + +include(${COMMON_ZEPHYR_LINKER_DIR}/debug-sections.cmake) diff --git a/soc/arm/nxp_imx/rt/CMakeLists.txt b/soc/arm/nxp_imx/rt/CMakeLists.txt index 9446f00bdc2..dd85c46f741 100644 --- a/soc/arm/nxp_imx/rt/CMakeLists.txt +++ b/soc/arm/nxp_imx/rt/CMakeLists.txt @@ -8,3 +8,25 @@ zephyr_sources_ifdef(CONFIG_SOC_SERIES_IMX_RT10XX soc_rt10xx.c) zephyr_linker_sources_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER ROM_START SORT_KEY 0 boot_header.ld) + +zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.conf" + OFFSET ${CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET} + KEEP + PRIO 10 +) + +if(CONFIG_DEVICE_CONFIGURATION_DATA) + set(boot_hdr_dcd_data_section ".boot_hdr.dcd_data") +endif() + +zephyr_linker_section_configure( + SECTION .rom_start + INPUT ".boot_hdr.ivt" + ".boot_hdr.data" + ${boot_hdr_dcd_data_section} + OFFSET ${CONFIG_IMAGE_VECTOR_TABLE_OFFSET} + KEEP + PRIO 11 +)