From c27d1c88b45ac466af14798dca835f18c64d82d9 Mon Sep 17 00:00:00 2001 From: Jon Medhurst Date: Fri, 6 Jan 2017 13:59:03 +0000 Subject: [PATCH] mps2: Add defines and devices for FPGA system control block These are fixed I/O registers for getting and setting the states of LEDs, buttons, SPI chip-selects, and LCD control lines. It also contains several free-running counters with no specific use. Change-Id: Ib49306d5501574f7eb354165cdca6f29e3d4dad4 Signed-off-by: Jon Medhurst --- arch/arm/soc/arm/mps2/Kconfig.series | 1 + arch/arm/soc/arm/mps2/soc.c | 10 +++++ arch/arm/soc/arm/mps2/soc_devices.h | 8 ++++ arch/arm/soc/arm/mps2/soc_memory_map.h | 8 +++- arch/arm/soc/arm/mps2/soc_registers.h | 55 ++++++++++++++++++++++++++ boards/arm/mps2_an385/board.h | 20 ++++++++++ 6 files changed, 100 insertions(+), 2 deletions(-) diff --git a/arch/arm/soc/arm/mps2/Kconfig.series b/arch/arm/soc/arm/mps2/Kconfig.series index 121c7c2738e..8509baae40c 100644 --- a/arch/arm/soc/arm/mps2/Kconfig.series +++ b/arch/arm/soc/arm/mps2/Kconfig.series @@ -10,5 +10,6 @@ config SOC_SERIES_MPS2 select SOC_FAMILY_ARM select CPU_CORTEX_M select CPU_HAS_SYSTICK + select GPIO_MMIO32 if GPIO help Enable support for ARM MPS2 MCU Series diff --git a/arch/arm/soc/arm/mps2/soc.c b/arch/arm/soc/arm/mps2/soc.c index 405b8b63778..e9855cef7f2 100644 --- a/arch/arm/soc/arm/mps2/soc.c +++ b/arch/arm/soc/arm/mps2/soc.c @@ -8,7 +8,17 @@ */ #include +#include #include +#include + +/* Setup GPIO drivers for accessing FPGAIO registers */ +GPIO_MMIO32_INIT(fpgaio_led0, FPGAIO_LED0_GPIO_NAME, + &__MPS2_FPGAIO->led0, FPGAIO_LED0_MASK); +GPIO_MMIO32_INIT(fpgaio_button, FPGAIO_BUTTON_GPIO_NAME, + &__MPS2_FPGAIO->button, FPGAIO_BUTTON_MASK); +GPIO_MMIO32_INIT(fpgaio_misc, FPGAIO_MISC_GPIO_NAME, + &__MPS2_FPGAIO->misc, FPGAIO_MISC_MASK); /** * @brief Perform basic hardware initialization at boot. diff --git a/arch/arm/soc/arm/mps2/soc_devices.h b/arch/arm/soc/arm/mps2/soc_devices.h index 41e9091f32a..5afa2b6171a 100644 --- a/arch/arm/soc/arm/mps2/soc_devices.h +++ b/arch/arm/soc/arm/mps2/soc_devices.h @@ -65,6 +65,14 @@ /* System Control Register (SYSCON) */ #define __MPS2_SYSCON ((volatile struct mps2_syscon *)SYSCON_BASE_ADDR) +/* FPGA system control block (FPGAIO) */ +#define __MPS2_FPGAIO ((volatile struct mps2_fpgaio *)FPGAIO_BASE_ADDR) + +/* Names of GPIO drivers used to provide access to some FPGAIO registers */ +#define FPGAIO_LED0_GPIO_NAME "FPGAIO_LED0" +#define FPGAIO_BUTTON_GPIO_NAME "FPGAIO_BUTTON" +#define FPGAIO_MISC_GPIO_NAME "FPGAIO_MISC" + #endif /* !_ASMLANGUAGE */ #endif /* _SOC_DEVICES_H_ */ diff --git a/arch/arm/soc/arm/mps2/soc_memory_map.h b/arch/arm/soc/arm/mps2/soc_memory_map.h index 643cbe42585..4fd95234dad 100644 --- a/arch/arm/soc/arm/mps2/soc_memory_map.h +++ b/arch/arm/soc/arm/mps2/soc_memory_map.h @@ -12,8 +12,9 @@ */ /* MPS2 Address space definition */ -#define MPS2_APB_BASE_ADDR 0x40000000 -#define MPS2_AHB_BASE_ADDR 0x40010000 +#define MPS2_APB_BASE_ADDR 0x40000000 +#define MPS2_AHB_BASE_ADDR 0x40010000 +#define MPS2_FPGA_APB_BASE_ADDR 0x40020000 /* MPS2 AHB peripherals */ #define GPIO_0_BASE_ADDR (MPS2_AHB_BASE_ADDR + 0x0000) @@ -33,4 +34,7 @@ #define WDOG_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x8000) #define UART_4_BASE_ADDR (MPS2_APB_BASE_ADDR + 0x9000) +/* MPS2 peripherals in FPGA APB subsystem */ +#define FPGAIO_BASE_ADDR (MPS2_FPGA_APB_BASE_ADDR + 0x8000) + #endif /* _SOC_MEMORY_MAP_H_ */ diff --git a/arch/arm/soc/arm/mps2/soc_registers.h b/arch/arm/soc/arm/mps2/soc_registers.h index 44f51c8d381..2ee96737733 100644 --- a/arch/arm/soc/arm/mps2/soc_registers.h +++ b/arch/arm/soc/arm/mps2/soc_registers.h @@ -12,6 +12,7 @@ #ifndef _ARM_MPS2_REGS_H_ #define _ARM_MPS2_REGS_H_ +#include #include /* System Control Register (SYSCON) */ @@ -28,4 +29,58 @@ struct mps2_syscon { volatile uint32_t rstinfo; }; +/* Registers in the FPGA system control block */ +struct mps2_fpgaio { + /* Offset: 0x000 LED connections */ + volatile uint32_t led0; + /* Offset: 0x004 RESERVED */ + volatile uint32_t reserved1; + /* Offset: 0x008 Buttons */ + volatile uint32_t button; + /* Offset: 0x00c RESERVED */ + volatile uint32_t reserved2; + /* Offset: 0x010 1Hz up counter */ + volatile uint32_t clk1hz; + /* Offset: 0x014 100Hz up counter */ + volatile uint32_t clk100hz; + /* Offset: 0x018 Cycle up counter */ + volatile uint32_t counter; + /* Offset: 0x01c Reload value for prescale counter */ + volatile uint32_t prescale; + /* Offset: 0x020 32-bit Prescale counter */ + volatile uint32_t pscntr; + /* Offset: 0x024 RESERVED */ + volatile uint32_t reserved3[10]; + /* Offset: 0x04c Misc control */ + volatile uint32_t misc; +}; + +/* Defines for bits in fpgaio led0 register */ +#define FPGAIO_LED0_USERLED0 0 +#define FPGAIO_LED0_USERLED1 1 + +/* Mask of valid bits in fpgaio led0 register */ +#define FPGAIO_LED0_MASK BIT_MASK(2) + +/* Defines for bits in fpgaio button register */ +#define FPGAIO_BUTTON_USERPB0 0 +#define FPGAIO_BUTTON_USERPB1 1 + +/* Mask of valid bits in fpgaio button register */ +#define FPGAIO_BUTTON_MASK BIT_MASK(2) + +/* Defines for bits in fpgaio misc register */ +#define FPGAIO_MISC_CLCD_CS 0 +#define FPGAIO_MISC_SPI_SS 1 +#define FPGAIO_MISC_CLCD_RESET 3 +#define FPGAIO_MISC_CLCD_RS 4 +#define FPGAIO_MISC_CLCD_RD 5 +#define FPGAIO_MISC_CLCD_BL_CTRL 6 +#define FPGAIO_MISC_ADC_SPI_CS 7 +#define FPGAIO_MISC_SHIELD0_SPI_CS 8 +#define FPGAIO_MISC_SHIELD1_SPI_CS 9 + +/* Mask of valid bits in fpgaio misc register */ +#define FPGAIO_MISC_MASK BIT_MASK(10) + #endif /* _ARM_MPS2_REGS_H_ */ diff --git a/boards/arm/mps2_an385/board.h b/boards/arm/mps2_an385/board.h index 56de65d89bb..c1ea3cf54f8 100644 --- a/boards/arm/mps2_an385/board.h +++ b/boards/arm/mps2_an385/board.h @@ -9,4 +9,24 @@ #include +#if defined(CONFIG_GPIO_MMIO32) + +/* USERLED0 */ +#define LED0_GPIO_PORT FPGAIO_LED0_GPIO_NAME +#define LED0_GPIO_PIN FPGAIO_LED0_USERLED0 + +/* USERLED1 */ +#define LED1_GPIO_PORT FPGAIO_LED0_GPIO_NAME +#define LED1_GPIO_PIN FPGAIO_LED0_USERLED1 + +/* USERPB0 */ +#define SW0_GPIO_NAME FPGAIO_BUTTON_GPIO_NAME +#define SW0_GPIO_PIN FPGAIO_BUTTON_USERPB0 + +/* USERPB1 */ +#define SW1_GPIO_NAME FPGAIO_BUTTON_GPIO_NAME +#define SW1_GPIO_PIN FPGAIO_BUTTON_USERPB1 + +#endif /* CONFIG_GPIO_MMIO32 */ + #endif /* __INC_BOARD_H */