From c229126f5545a59d76aa7b297830d7ddabcc5ef1 Mon Sep 17 00:00:00 2001 From: Daniel Leung Date: Fri, 19 Oct 2018 09:22:47 -0700 Subject: [PATCH] xtensa: intel_s1000: turn on XTENSA_ASM2 This adds the necessary bits to support ASM2 with XCC for Intel S1000 SoC. With ASM2 enabled, xcc is now required to build for Intel S1000 SoC. Signed-off-by: Daniel Leung --- boards/xtensa/intel_s1000_crb/board.cmake | 4 + soc/xtensa/intel_s1000/Kconfig.defconfig | 8 + .../intel_s1000/include/_soc_inthandlers.h | 257 ++++++++++++++++++ soc/xtensa/intel_s1000/linker.ld | 1 + 4 files changed, 270 insertions(+) create mode 100644 soc/xtensa/intel_s1000/include/_soc_inthandlers.h diff --git a/boards/xtensa/intel_s1000_crb/board.cmake b/boards/xtensa/intel_s1000_crb/board.cmake index d5a19ed5526..b838d7cfe8d 100644 --- a/boards/xtensa/intel_s1000_crb/board.cmake +++ b/boards/xtensa/intel_s1000_crb/board.cmake @@ -7,3 +7,7 @@ board_finalize_runner_args(intel_s1000 "--ocd-jtag-instr=dsp0_gdb.txt" "--gdb-flash-file=load_elf.txt" ) + +if(NOT "${ZEPHYR_TOOLCHAIN_VARIANT}" STREQUAL "xcc") + message(FATAL_ERROR "ZEPHYR_TOOLCHAIN_VARIANT != xcc. This requires xcc to build!") +endif() diff --git a/soc/xtensa/intel_s1000/Kconfig.defconfig b/soc/xtensa/intel_s1000/Kconfig.defconfig index 0286ba35e65..376867644aa 100644 --- a/soc/xtensa/intel_s1000/Kconfig.defconfig +++ b/soc/xtensa/intel_s1000/Kconfig.defconfig @@ -12,4 +12,12 @@ config SOC config IRQ_OFFLOAD_INTNUM default 0 +config XTENSA_ASM2 + def_bool y + +# S1000 does not have MISC0. +# Since EXCSAVE2 is unused by Zephyr, use it instead. +config XTENSA_KERNEL_CPU_PTR_SR + default "EXCSAVE2" + endif diff --git a/soc/xtensa/intel_s1000/include/_soc_inthandlers.h b/soc/xtensa/intel_s1000/include/_soc_inthandlers.h new file mode 100644 index 00000000000..f70d3d68c90 --- /dev/null +++ b/soc/xtensa/intel_s1000/include/_soc_inthandlers.h @@ -0,0 +1,257 @@ +/* + * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT. + * + * Functions here are designed to produce efficient code to + * search an Xtensa bitmask of interrupts, inspecting only those bits + * declared to be associated with a given interrupt level. Each + * dispatcher will handle exactly one flagged interrupt, in numerical + * order (low bits first) and will return a mask of that bit that can + * then be cleared by the calling code. Unrecognized bits for the + * level will invoke an error handler. + */ + +#include +#include + +#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 1 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 2 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT9_LEVEL) || XCHAL_INT9_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT10_LEVEL) || XCHAL_INT10_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT11_LEVEL) || XCHAL_INT11_LEVEL != 3 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT12_LEVEL) || XCHAL_INT12_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT13_LEVEL) || XCHAL_INT13_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT14_LEVEL) || XCHAL_INT14_LEVEL != 4 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT15_LEVEL) || XCHAL_INT15_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT16_LEVEL) || XCHAL_INT16_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT17_LEVEL) || XCHAL_INT17_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT18_LEVEL) || XCHAL_INT18_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT19_LEVEL) || XCHAL_INT19_LEVEL != 5 +#error core-isa.h interrupt level does not match dispatcher! +#endif +#if !defined(XCHAL_INT20_LEVEL) || XCHAL_INT20_LEVEL != 7 +#error core-isa.h interrupt level does not match dispatcher! +#endif + +static inline int _xtensa_handle_one_int1(unsigned int mask) +{ + if (mask & 0x3) { + if (mask & (1 << 0)) { + struct _isr_table_entry *e = &_sw_isr_table[0]; + + e->isr(e->arg); + return 1 << 0; + } + if (mask & (1 << 1)) { + struct _isr_table_entry *e = &_sw_isr_table[1]; + + e->isr(e->arg); + return 1 << 1; + } + } else { + if (mask & (1 << 2)) { + struct _isr_table_entry *e = &_sw_isr_table[2]; + + e->isr(e->arg); + return 1 << 2; + } + if (mask & (1 << 3)) { + struct _isr_table_entry *e = &_sw_isr_table[3]; + + e->isr(e->arg); + return 1 << 3; + } + } + return 0; +} + +static inline int _xtensa_handle_one_int2(unsigned int mask) +{ + if (mask & 0x30) { + if (mask & (1 << 4)) { + struct _isr_table_entry *e = &_sw_isr_table[4]; + + e->isr(e->arg); + return 1 << 4; + } + if (mask & (1 << 5)) { + struct _isr_table_entry *e = &_sw_isr_table[5]; + + e->isr(e->arg); + return 1 << 5; + } + } else { + if (mask & (1 << 6)) { + struct _isr_table_entry *e = &_sw_isr_table[6]; + + e->isr(e->arg); + return 1 << 6; + } + if (mask & (1 << 7)) { + struct _isr_table_entry *e = &_sw_isr_table[7]; + + e->isr(e->arg); + return 1 << 7; + } + } + return 0; +} + +static inline int _xtensa_handle_one_int3(unsigned int mask) +{ + if (mask & 0x300) { + if (mask & (1 << 8)) { + struct _isr_table_entry *e = &_sw_isr_table[8]; + + e->isr(e->arg); + return 1 << 8; + } + if (mask & (1 << 9)) { + struct _isr_table_entry *e = &_sw_isr_table[9]; + + e->isr(e->arg); + return 1 << 9; + } + } else { + if (mask & (1 << 10)) { + struct _isr_table_entry *e = &_sw_isr_table[10]; + + e->isr(e->arg); + return 1 << 10; + } + if (mask & (1 << 11)) { + struct _isr_table_entry *e = &_sw_isr_table[11]; + + e->isr(e->arg); + return 1 << 11; + } + } + return 0; +} + +static inline int _xtensa_handle_one_int4(unsigned int mask) +{ + if (mask & (1 << 12)) { + struct _isr_table_entry *e = &_sw_isr_table[12]; + + e->isr(e->arg); + return 1 << 12; + } + if (mask & (1 << 13)) { + struct _isr_table_entry *e = &_sw_isr_table[13]; + + e->isr(e->arg); + return 1 << 13; + } + if (mask & (1 << 14)) { + struct _isr_table_entry *e = &_sw_isr_table[14]; + + e->isr(e->arg); + return 1 << 14; + } + return 0; +} + +static inline int _xtensa_handle_one_int5(unsigned int mask) +{ + if (mask & 0x18000) { + if (mask & (1 << 15)) { + struct _isr_table_entry *e = &_sw_isr_table[15]; + + e->isr(e->arg); + return 1 << 15; + } + if (mask & (1 << 16)) { + struct _isr_table_entry *e = &_sw_isr_table[16]; + + e->isr(e->arg); + return 1 << 16; + } + } else { + if (mask & (1 << 17)) { + struct _isr_table_entry *e = &_sw_isr_table[17]; + + e->isr(e->arg); + return 1 << 17; + } + if (mask & (1 << 18)) { + struct _isr_table_entry *e = &_sw_isr_table[18]; + + e->isr(e->arg); + return 1 << 18; + } + if (mask & (1 << 19)) { + struct _isr_table_entry *e = &_sw_isr_table[19]; + + e->isr(e->arg); + return 1 << 19; + } + } + return 0; +} + +static inline int _xtensa_handle_one_int7(unsigned int mask) +{ + if (mask & (1 << 20)) { + struct _isr_table_entry *e = &_sw_isr_table[20]; + + e->isr(e->arg); + return 1 << 20; + } + return 0; +} + +static inline int _xtensa_handle_one_int0(unsigned int mask) +{ + return 0; +} + +static inline int _xtensa_handle_one_int6(unsigned int mask) +{ + return 0; +} + diff --git a/soc/xtensa/intel_s1000/linker.ld b/soc/xtensa/intel_s1000/linker.ld index b7d2f7932b6..23fe5a93fdd 100644 --- a/soc/xtensa/intel_s1000/linker.ld +++ b/soc/xtensa/intel_s1000/linker.ld @@ -315,6 +315,7 @@ SECTIONS _text_start = ABSOLUTE(.); *(.entry.text) *(.init.literal) + *(.iram0.text) KEEP(*(.init)) *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*) *(.fini.literal)