soc: npcx: add support for npcx9m7fb

Add new SoC npcx9m7fb support for npcx9 series.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>

dts/arm/nuvoton/npcx9m7fb.dtsi

@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2023 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include "npcx/npcx9.dtsi"
+
+/ {
+	flash0: flash@10070000 {
+		reg = <0x10070000 DT_SIZE_K(320)>;
+	};
+
+	flash1: flash@64000000 {
+		reg = <0x64000000 DT_SIZE_K(1024)>;
+	};
+
+	sram0: memory@200c0000 {
+		compatible = "mmio-sram";
+		reg = <0x200C0000 DT_SIZE_K(64)>;
+	};
+
+	soc-id {
+		device-id = <0x62>;
+	};
+};
+
+&qspi_fiu0 {
+	int_flash: w25q80@0 {
+		compatible ="nuvoton,npcx-fiu-nor";
+		size = <DT_SIZE_M(1 * 8)>;
+		reg = <0>;
+		status = "okay";
+
+		/* quad spi bus configuration of nor flash device */
+		qspi-flags = <NPCX_QSPI_SW_CS1>;
+		mapped-addr = <0x64000000>;
+		pinctrl-0 = <&int_flash_sl>;
+		pinctrl-names = "default";
+	};
+};

soc/nuvoton/npcx/Kconfig

@@ -35,7 +35,7 @@ config NPCX_HEADER_CHIP
 	default "npcx7m7" if SOC_NPCX7M7FC
 	default "npcx9m3" if SOC_NPCX9M3F
 	default "npcx9m6" if SOC_NPCX9M6F
-	default "npcx9m7" if SOC_NPCX9M7F
+	default "npcx9m7" if SOC_NPCX9M7F || SOC_NPCX9M7FB
 	default "npcx9mfp" if SOC_NPCX9MFP
 	default "npcx4m3" if SOC_NPCX4M3F
 	default "npcx4m8" if SOC_NPCX4M8F

soc/nuvoton/npcx/npcx9/Kconfig.soc

@@ -27,6 +27,12 @@ config SOC_NPCX9M7F
 	help
 	  NPCX9M7F
 
+config SOC_NPCX9M7FB
+	bool
+	select SOC_SERIES_NPCX9
+	help
+	  NPCX9M7FB
+
 config SOC_NPCX9MFP
 	bool
 	select SOC_SERIES_NPCX9
@@ -40,4 +46,5 @@ config SOC
 	default "npcx9m3f" if SOC_NPCX9M3F
 	default "npcx9m6f" if SOC_NPCX9M6F
 	default "npcx9m7f" if SOC_NPCX9M7F
+	default "npcx9m7fb" if SOC_NPCX9M7FB
 	default "npcx9mfp" if SOC_NPCX9MFP

soc/nuvoton/npcx/soc.yml

@@ -15,4 +15,5 @@ family:
     - name: npcx9m3f
     - name: npcx9m6f
     - name: npcx9m7f
+    - name: npcx9m7fb
     - name: npcx9mfp