diff --git a/dts/arm/st/u5/stm32u5a5.dtsi b/dts/arm/st/u5/stm32u5a5.dtsi
new file mode 100644
index 00000000000..bc8ba619020
--- /dev/null
+++ b/dts/arm/st/u5/stm32u5a5.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/u5/stm32u595.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32u5a5", "st,stm32u5", "simple-bus";
+	};
+};
diff --git a/dts/arm/st/u5/stm32u5a5Xj.dtsi b/dts/arm/st/u5/stm32u5a5Xj.dtsi
new file mode 100644
index 00000000000..6719e89619d
--- /dev/null
+++ b/dts/arm/st/u5/stm32u5a5Xj.dtsi
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2023 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/u5/stm32u5a5.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		/* SRAM1 + SRAM2 + SRAM3 + SRAM5 */
+		reg = <0x20000000 DT_SIZE_K(2496)>;
+	};
+	sram1: memory@28000000 {
+		/* SRAM4 */
+		reg = <0x28000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(4)>;
+			};
+		};
+	};
+};