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drivers/dai/intel/ssp: Get number of SSP ports from Kconfig

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Instead of using SoC versions, define the information about base and
extended ports on Kconfig, and use this information from there.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
This commit is contained in:
Ederson de Souza 2022-07-28 10:09:09 -07:00 • committed by Anas Nashif
commit c1dc2683b9
4 changed files with 22 additions and 17 deletions
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8
drivers/dai/intel/ssp/Kconfig.ssp
View file

@ -22,4 +22,12 @@ if DAI_INTEL_SSP
config DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING config DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING
bool bool
config DAI_INTEL_SSP_NUM_BASE
int
default 6
config DAI_INTEL_SSP_NUM_EXT
int
default 0
endif endif

10
drivers/dai/intel/ssp/ssp.c
View file

@ -681,9 +681,10 @@ static inline void dai_ssp_pm_runtime_dis_ssp_clk_gating(struct dai_intel_ssp *d
uint32_t shim_reg; uint32_t shim_reg;
shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) | shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) |
(index < DAI_INTEL_SSP_NUM_BASE ? (index < CONFIG_DAI_INTEL_SSP_NUM_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) : SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index - DAI_INTEL_SSP_NUM_BASE)); SHIM_CLKCTL_I2SEFDCGB(index -
CONFIG_DAI_INTEL_SSP_NUM_BASE));
sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL); sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL);
@ -697,9 +698,10 @@ static inline void dai_ssp_pm_runtime_en_ssp_clk_gating(struct dai_intel_ssp *dp
uint32_t shim_reg; uint32_t shim_reg;
shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) & shim_reg = sys_read32(dai_shim_base(dp) + SHIM_CLKCTL) &
~(index < DAI_INTEL_SSP_NUM_BASE ? ~(index < CONFIG_DAI_INTEL_SSP_NUM_BASE ?
SHIM_CLKCTL_I2SFDCGB(index) : SHIM_CLKCTL_I2SFDCGB(index) :
SHIM_CLKCTL_I2SEFDCGB(index - DAI_INTEL_SSP_NUM_BASE)); SHIM_CLKCTL_I2SEFDCGB(index -
CONFIG_DAI_INTEL_SSP_NUM_BASE));
sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL); sys_write32(shim_reg, dai_shim_base(dp) + SHIM_CLKCTL);

15
drivers/dai/intel/ssp/ssp.h
View file

@ -40,18 +40,6 @@
#define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY 12 #define DAI_INTEL_SSP_PLATFORM_DEFAULT_DELAY 12
#define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8 #define DAI_INTEL_SSP_DEFAULT_TRY_TIMES 8
#if CONFIG_SOC_INTEL_CAVS_V15
/** \brief Number of 'base' SSP ports available */
#define DAI_INTEL_SSP_NUM_BASE 4
/** \brief Number of 'extended' SSP ports available */
#define DAI_INTEL_SSP_NUM_EXT 2
#else
/** \brief Number of 'base' SSP ports available */
#define DAI_INTEL_SSP_NUM_BASE 6
/** \brief Number of 'extended' SSP ports available */
#define DAI_INTEL_SSP_NUM_EXT 0
#endif
/** \brief Number of SSP MCLKs available */ /** \brief Number of SSP MCLKs available */
#define DAI_INTEL_SSP_NUM_MCLK 2 #define DAI_INTEL_SSP_NUM_MCLK 2
@ -288,7 +276,8 @@ struct dai_intel_ssp_mn {
int mclk_source_clock; int mclk_source_clock;
#if CONFIG_INTEL_MN #if CONFIG_INTEL_MN
enum bclk_source bclk_sources[(DAI_INTEL_SSP_NUM_BASE + DAI_INTEL_SSP_NUM_EXT)]; enum bclk_source bclk_sources[(CONFIG_DAI_INTEL_SSP_NUM_BASE +
CONFIG_DAI_INTEL_SSP_NUM_EXT)];
int bclk_source_mn_clock; int bclk_source_mn_clock;
#endif #endif

6
soc/xtensa/intel_adsp/cavs/Kconfig.defconfig.cavs_v15
View file

@ -38,6 +38,12 @@ if DAI_INTEL_SSP
config DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING config DAI_SSP_CLK_FORCE_DYNAMIC_CLOCK_GATING
default y default y
config DAI_INTEL_SSP_NUM_BASE
default 4
config DAI_INTEL_SSP_NUM_EXT
default 2
endif # DAI_INTEL_SSP endif # DAI_INTEL_SSP
endif endif