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soc: nordic: dmm: Fix DMM_REG_ALIGN_SIZE macro when CONFIG_DCACHE=n

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Make sure this expansion doesn't include `CONFIG_DCACHE_LINE_SIZE`,
which would be undefined and produce a build error.

Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
This commit is contained in:
Grzegorz Swiderski 2024-10-31 11:54:12 +01:00 • committed by Mahesh Mahadevan
commit c1776df8ae
1 changed files with 13 additions and 5 deletions
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18
soc/nordic/common/dmm.h
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@ -23,12 +23,13 @@ extern "C" {
/** @cond INTERNAL_HIDDEN */
#ifdef CONFIG_DCACHE
/* Determine if memory region is cacheable. */
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(CONFIG_DCACHE, \
(COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))), (0))
#define DMM_IS_REG_CACHEABLE(node_id) \
COND_CODE_1(DT_NODE_HAS_PROP(node_id, zephyr_memory_attr), \
((DT_PROP(node_id, zephyr_memory_attr) & DT_MEM_CACHEABLE)), \
(0))
/* Determine required alignment of the data buffers in specified memory region.
* Cache line alignment is required if region is cacheable and data cache is enabled.
@ -36,6 +37,13 @@ extern "C" {
#define DMM_REG_ALIGN_SIZE(node_id) \
(DMM_IS_REG_CACHEABLE(node_id) ? CONFIG_DCACHE_LINE_SIZE : sizeof(uint8_t))
#else
#define DMM_IS_REG_CACHEABLE(node_id) 0
#define DMM_REG_ALIGN_SIZE(node_id) (sizeof(uint8_t))
#endif /* CONFIG_DCACHE */
/* Determine required alignment of the data buffers in memory region
* associated with specified device node.
*/