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boards: stm32f429i_disc1: add sdram support

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Add support for the 8MB SDRAM found in STM32F429-DISC1 boards.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit is contained in:
Fabio Baltieri 2021-06-05 21:56:22 +01:00 • committed by Anas Nashif
commit c10acf3c61
2 changed files with 45 additions and 0 deletions
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2
boards/arm/stm32f429i_disc1/doc/index.rst
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@ -97,6 +97,8 @@ The Zephyr stm32f429i_disc1 board configuration supports the following hardware
+-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
| FMC | on-chip | memc (SDRAM) |
+-----------+------------+-------------------------------------+
Other hardware features are not yet supported on Zephyr porting.

43
boards/arm/stm32f429i_disc1/stm32f429i_disc1.dts
View file

@ -20,6 +20,11 @@
zephyr,ccm = &ccm0;
};
sdram2: sdram@d0000000 {
device_type = "memory";
reg = <0xd0000000 DT_SIZE_M(8)>;
};
leds {
compatible = "gpio-leds";
orange_led_3: led_3 {
@ -109,3 +114,41 @@
cmd-data-gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
};
};
&fmc {
status = "okay";
pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
&fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke1_pb5
&fmc_sdne1_pb6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
&fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3
&fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13
&fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
&fmc_a12_pg2 &fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5
&fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
&fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
&fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
&fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
sdram {
status = "okay";
power-up-delay = <100>;
num-auto-refresh = <1>;
mode-register = <0>;
refresh-rate = <1386>;
bank@1 {
reg = <1>;
st,sdram-control = <STM32_FMC_SDRAM_NC_8
STM32_FMC_SDRAM_NR_12
STM32_FMC_SDRAM_MWID_16
STM32_FMC_SDRAM_NB_4
STM32_FMC_SDRAM_CAS_2
STM32_FMC_SDRAM_SDCLK_PERIOD_3
STM32_FMC_SDRAM_RBURST_DISABLE
STM32_FMC_SDRAM_RPIPE_1>;
st,sdram-timing = <2 7 4 7 2 2 2>;
};
};
};