adc: adc dma driver
add dma support to adc driver add HW trigger dma support using new dma api to request dma channel tested on frdm_k82f and frdm_k64f Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
This commit is contained in:
parent
d7edd375bd
commit
c1080f3ceb
2 changed files with 230 additions and 15 deletions
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@ -53,6 +53,28 @@ config ADC_MCUX_ADC16_VREF_ALTERNATE
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endchoice
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config ADC_MCUX_ADC16_ENABLE_EDMA
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bool "Enable EDMA for adc driver"
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depends on HAS_MCUX_ADC16 && HAS_MCUX_EDMA
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help
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Enable the MCUX ADC16 driver.
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if ADC_MCUX_ADC16_ENABLE_EDMA
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config ADC_MCUX_ADC16_INIT_PRIORITY
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int "Init priority"
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default 70
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help
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Device driver initialization priority.
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config ADC_MCUX_ADC16_HW_TRIGGER
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bool "ADC HW TRIGGER"
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default y
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help
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Support HW Trigger ADC
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endif # ADC_MCUX_ADC16_ENABLE_EDMA
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endif # ADC_MCUX_ADC16
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2018, NXP
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* Copyright (c) 2017-2018, 2020, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -8,6 +8,11 @@
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#include <errno.h>
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#include <drivers/adc.h>
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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#include <drivers/dma.h>
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#include <fsl_sim.h>
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#endif
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#include <fsl_adc16.h>
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#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
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@ -19,19 +24,82 @@ LOG_MODULE_REGISTER(adc_mcux_adc16);
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struct mcux_adc16_config {
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ADC_Type *base;
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#ifndef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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void (*irq_config_func)(const struct device *dev);
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#endif
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uint32_t clk_source; /* ADC clock source selection */
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uint32_t long_sample; /* ADC long sample mode selection */
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uint32_t hw_trigger_src; /* ADC hardware trigger source */
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/* defined in SIM module SOPT7 */
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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uint32_t dma_slot; /* ADC DMA MUX slot */
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#endif
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uint32_t trg_offset;
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uint32_t trg_bits;
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uint32_t alt_offset;
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uint32_t alt_bits;
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bool periodic_trigger; /* ADC enable periodic trigger */
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bool channel_mux_b;
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bool high_speed; /* ADC enable high speed mode*/
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bool continuous_convert; /* ADC enable continuous convert*/
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};
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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struct adc_edma_config {
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int32_t state;
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uint32_t dma_channel;
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void (*irq_call_back)(void);
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struct dma_config dma_cfg;
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struct dma_block_config dma_block;
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};
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#endif
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struct mcux_adc16_data {
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const struct device *dev;
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struct adc_context ctx;
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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const struct device *dev_dma;
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struct adc_edma_config adc_dma_config;
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#endif
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint32_t channels;
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uint8_t channel_id;
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};
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#define DEV_CFG(dev) ((const struct mcux_adc16_config *const)dev->config)
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#define DEV_DATA(dev) ((struct mcux_adc16_data *)dev->data)
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#define DEV_BASE(dev) ((ADC_Type *)DEV_CFG(dev)->base)
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#ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
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#define SIM_SOPT7_ADCSET(x, shifts, mask) \
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(((uint32_t)(((uint32_t)(x)) << shifts)) & mask)
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#endif
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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static void adc_dma_callback(const struct device *dma_dev, void *callback_arg,
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uint32_t channel, int error_code)
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{
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struct device *dev = (struct device *)callback_arg;
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struct mcux_adc16_data *data = DEV_DATA(dev);
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LOG_DBG("DMA done");
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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#endif
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#ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
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static void adc_hw_trigger_enable(const struct device *dev)
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{
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const struct mcux_adc16_config *config = dev->config;
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/* enable ADC trigger channel */
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SIM->SOPT7 |= SIM_SOPT7_ADCSET(config->hw_trigger_src,
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config->trg_offset, config->trg_bits) |
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SIM_SOPT7_ADCSET(1, config->alt_offset, config->alt_bits);
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}
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#endif
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static int mcux_adc16_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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@ -62,6 +130,10 @@ static int mcux_adc16_channel_setup(const struct device *dev,
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return -EINVAL;
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}
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#ifdef CONFIG_ADC_MCUX_ADC16_HW_TRIGGER
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adc_hw_trigger_enable(dev);
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#endif
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return 0;
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}
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@ -89,7 +161,8 @@ static int start_read(const struct device *dev,
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case 13:
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resolution = kADC16_Resolution12or13Bit;
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break;
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#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && (FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
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#if defined(FSL_FEATURE_ADC16_MAX_RESOLUTION) && \
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(FSL_FEATURE_ADC16_MAX_RESOLUTION >= 16U)
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case 16:
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resolution = kADC16_Resolution16Bit;
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break;
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@ -130,6 +203,9 @@ static int start_read(const struct device *dev,
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adc_context_start_read(&data->ctx, sequence);
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error = adc_context_wait_for_completion(&data->ctx);
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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dma_stop(data->dev_dma, data->adc_dma_config.dma_channel);
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#endif
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return error;
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}
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@ -180,6 +256,11 @@ static void mcux_adc16_start_channel(const struct device *dev)
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channel_config.enableInterruptOnConversionCompleted = true;
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channel_config.channelNumber = data->channel_id;
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ADC16_SetChannelConfig(config->base, channel_group, &channel_config);
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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LOG_DBG("Starting EDMA");
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dma_start(data->dev_dma, data->adc_dma_config.dma_channel);
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#endif
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LOG_DBG("Starting channel done");
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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@ -190,6 +271,17 @@ static void adc_context_start_sampling(struct adc_context *ctx)
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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LOG_DBG("config dma");
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data->buffer = ctx->sequence.buffer;
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data->adc_dma_config.dma_block.block_size = ctx->sequence.buffer_size;
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data->adc_dma_config.dma_block.dest_address = (uint32_t)data->buffer;
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data->adc_dma_config.dma_cfg.head_block =
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&(data->adc_dma_config.dma_block);
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dma_config(data->dev_dma, data->adc_dma_config.dma_channel,
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&data->adc_dma_config.dma_cfg);
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#endif
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mcux_adc16_start_channel(data->dev);
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}
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@ -204,6 +296,7 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
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}
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}
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#ifndef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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static void mcux_adc16_isr(const struct device *dev)
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{
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const struct mcux_adc16_config *config = dev->config;
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@ -213,8 +306,8 @@ static void mcux_adc16_isr(const struct device *dev)
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uint16_t result;
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result = ADC16_GetChannelConversionValue(base, channel_group);
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LOG_DBG("Finished channel %d. Result is 0x%04x",
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data->channel_id, result);
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LOG_DBG("Finished channel %d. Result is 0x%04x", data->channel_id,
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result);
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*data->buffer++ = result;
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data->channels &= ~BIT(data->channel_id);
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adc_context_on_sampling_done(&data->ctx, dev);
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}
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}
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#endif
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static int mcux_adc16_init(const struct device *dev)
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{
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ADC_Type *base = config->base;
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adc16_config_t adc_config;
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LOG_DBG("init adc");
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ADC16_GetDefaultConfig(&adc_config);
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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adc_config.clockSource = (adc16_clock_source_t)config->clk_source;
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adc_config.longSampleMode =
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(adc16_long_sample_mode_t)config->long_sample;
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adc_config.enableHighSpeed = config->high_speed;
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adc_config.enableContinuousConversion = config->continuous_convert;
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#endif
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#if CONFIG_ADC_MCUX_ADC16_VREF_DEFAULT
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adc_config.referenceVoltageSource = kADC16_ReferenceVoltageSourceVref;
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#else /* CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE */
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if (config->channel_mux_b) {
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ADC16_SetChannelMuxMode(base, kADC16_ChannelMuxB);
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}
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ADC16_EnableHardwareTrigger(base, false);
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config->irq_config_func(dev);
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if (IS_ENABLED(CONFIG_ADC_MCUX_ADC16_HW_TRIGGER)) {
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ADC16_EnableHardwareTrigger(base, true);
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} else {
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ADC16_EnableHardwareTrigger(base, false);
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}
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data->dev = dev;
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/* dma related init */
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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/* Enable DMA. */
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ADC16_EnableDMA(base, true);
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data->adc_dma_config.dma_cfg.block_count = 1U;
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data->adc_dma_config.dma_cfg.dma_slot = config->dma_slot;
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data->adc_dma_config.dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
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data->adc_dma_config.dma_cfg.source_burst_length = 4U;
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data->adc_dma_config.dma_cfg.dest_burst_length = 4U;
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data->adc_dma_config.dma_cfg.channel_priority = 0U;
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data->adc_dma_config.dma_cfg.dma_callback = adc_dma_callback;
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data->adc_dma_config.dma_cfg.user_data = (void *)dev;
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data->adc_dma_config.dma_cfg.source_data_size = 4U;
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data->adc_dma_config.dma_cfg.dest_data_size = 4U;
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data->adc_dma_config.dma_block.source_address = (uint32_t)&base->R[0];
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if (data->dev_dma == NULL || !device_is_ready(data->dev_dma)) {
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LOG_ERR("dma binding fail");
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return -EINVAL;
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}
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if (config->periodic_trigger) {
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enum dma_channel_filter adc_filter = DMA_CHANNEL_PERIODIC;
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data->adc_dma_config.dma_channel =
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dma_request_channel(data->dev_dma, (void *)&adc_filter);
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} else {
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enum dma_channel_filter adc_filter = DMA_CHANNEL_NORMAL;
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data->adc_dma_config.dma_channel =
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dma_request_channel(data->dev_dma, (void *)&adc_filter);
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}
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if (data->adc_dma_config.dma_channel == -EINVAL) {
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LOG_ERR("can not allocate dma channel");
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return -EINVAL;
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}
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LOG_DBG("dma allocated channel %d", data->adc_dma_config.dma_channel);
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#else
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config->irq_config_func(dev);
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#endif
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LOG_INF("adc init done");
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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#endif
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};
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#define ACD16_MCUX_INIT(n) \
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static void mcux_adc16_config_func_##n(const struct device *dev); \
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\
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#ifdef CONFIG_ADC_MCUX_ADC16_ENABLE_EDMA
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#define ACD16_MCUX_INIT(n) \
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static const struct mcux_adc16_config mcux_adc16_config_##n = { \
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.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = mcux_adc16_config_func_##n, \
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.channel_mux_b = DT_INST_PROP(n, channel_mux_b), \
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.clk_source = DT_INST_PROP_OR(n, clk_source, 0), \
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.long_sample = DT_INST_PROP_OR(n, long_sample, 0), \
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.high_speed = DT_INST_PROP(n, high_speed), \
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.periodic_trigger = DT_INST_PROP(n, periodic_trigger), \
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.continuous_convert = \
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DT_INST_PROP(n, continuous_convert), \
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.hw_trigger_src = \
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DT_INST_PROP_OR(n, hw_trigger_src, 0), \
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.dma_slot = DT_INST_DMAS_CELL_BY_IDX(n, 0, source), \
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.trg_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, offset), \
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.trg_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 0, bits), \
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.alt_offset = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, offset), \
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.alt_bits = DT_INST_CLOCKS_CELL_BY_IDX(n, 1, bits), \
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}; \
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\
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static struct mcux_adc16_data mcux_adc16_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(mcux_adc16_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(mcux_adc16_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(mcux_adc16_data_##n, ctx), \
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.dev_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, adc##n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &mcux_adc16_init, \
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NULL, &mcux_adc16_data_##n, \
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&mcux_adc16_config_##n, POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&mcux_adc16_driver_api); \
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DEVICE_DT_INST_DEFINE(n, &mcux_adc16_init, \
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NULL, \
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&mcux_adc16_data_##n, \
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&mcux_adc16_config_##n, \
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POST_KERNEL, \
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CONFIG_ADC_MCUX_ADC16_INIT_PRIORITY, \
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&mcux_adc16_driver_api);
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#else
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#define ACD16_MCUX_INIT(n) \
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static void mcux_adc16_config_func_##n(const struct device *dev); \
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static const struct mcux_adc16_config mcux_adc16_config_##n = { \
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.base = (ADC_Type *)DT_INST_REG_ADDR(n), \
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.irq_config_func = mcux_adc16_config_func_##n, \
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.channel_mux_b = DT_INST_PROP(n, channel_mux_b), \
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.clk_source = DT_INST_PROP_OR(n, clk_source, 0), \
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.long_sample = DT_INST_PROP_OR(n, long_sample, 0), \
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.high_speed = DT_INST_PROP(n, high_speed), \
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.continuous_convert = \
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DT_INST_PROP(n, continuous_convert), \
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}; \
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static struct mcux_adc16_data mcux_adc16_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(mcux_adc16_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(mcux_adc16_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(mcux_adc16_data_##n, ctx), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &mcux_adc16_init, \
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NULL, \
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&mcux_adc16_data_##n, \
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&mcux_adc16_config_##n, \
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POST_KERNEL, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&mcux_adc16_driver_api); \
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\
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static void mcux_adc16_config_func_##n(const struct device *dev) \
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{ \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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#endif
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DT_INST_FOREACH_STATUS_OKAY(ACD16_MCUX_INIT)
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