diff --git a/boards/arm/mimxrt1160_evk/CMakeLists.txt b/boards/arm/mimxrt1160_evk/CMakeLists.txt new file mode 100644 index 00000000000..7f5e92617d0 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/CMakeLists.txt @@ -0,0 +1,8 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_library() +zephyr_library_sources(pinmux.c) diff --git a/boards/arm/mimxrt1160_evk/Kconfig.board b/boards/arm/mimxrt1160_evk/Kconfig.board new file mode 100644 index 00000000000..2f7b3533bf7 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/Kconfig.board @@ -0,0 +1,12 @@ +# Copyright (c) 2021, NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT1160_EVK_CM7 + bool "NXP MIMXRT1160-EVK CM7" + depends on SOC_MIMXRT1166_CM7 + select SOC_PART_NUMBER_MIMXRT1166DVM6A + +config BOARD_MIMXRT1160_EVK_CM4 + bool "NXP MIMXRT1160-EVK CM4" + depends on SOC_MIMXRT1166_CM4 + select SOC_PART_NUMBER_MIMXRT1166DVM6A diff --git a/boards/arm/mimxrt1160_evk/Kconfig.defconfig b/boards/arm/mimxrt1160_evk/Kconfig.defconfig new file mode 100644 index 00000000000..fb5f65cb7bd --- /dev/null +++ b/boards/arm/mimxrt1160_evk/Kconfig.defconfig @@ -0,0 +1,21 @@ +# MIMXRT1160-EVK board + +# Copyright (c) 2021, NXP +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 + +config BOARD + default "mimxrt1160_evk_cm7" if BOARD_MIMXRT1160_EVK_CM7 + default "mimxrt1160_evk_cm4" if BOARD_MIMXRT1160_EVK_CM4 + +choice CODE_LOCATION + default CODE_FLEXSPI if BOARD_MIMXRT1160_EVK_CM7 + default CODE_SRAM0 if BOARD_MIMXRT1160_EVK_CM4 +endchoice + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 240000000 if BOARD_MIMXRT1160_EVK_CM4 && CORTEX_M_SYSTICK + default 600000000 if BOARD_MIMXRT1160_EVK_CM7 && CORTEX_M_SYSTICK + +endif # BOARD_MIMXRT1160_EVK_CM7 || BOARD_MIMXRT1160_EVK_CM4 diff --git a/boards/arm/mimxrt1160_evk/board.cmake b/boards/arm/mimxrt1160_evk/board.cmake new file mode 100644 index 00000000000..cfbdb0ac9ba --- /dev/null +++ b/boards/arm/mimxrt1160_evk/board.cmake @@ -0,0 +1,11 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +board_runner_args(pyocd "--target=mimxrt1160_cm7") +board_runner_args(jlink "--device=MIMXRT1166xxx6_M7" "--reset-after-load") + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake) diff --git a/boards/arm/mimxrt1160_evk/doc/index.rst b/boards/arm/mimxrt1160_evk/doc/index.rst new file mode 100644 index 00000000000..de176d92266 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/doc/index.rst @@ -0,0 +1,230 @@ +.. _mimxrt1160_evk: + +NXP MIMXRT1160-EVK +################## + +Overview +******** + +The dual core i.MX RT1160 runs on the Cortex-M7 core at 600 MHz and on the +Cortex-M4 at 240 MHz. The i.MX RT1160 MCU offers support over a wide +temperature range and is qualified for consumer, industrial and automotive +markets. + +.. image:: ./mimxrt1160_evk.jpg + :width: 600px + :align: center + :alt: MIMXRT1160-EVK + +Hardware +******** + +- MIMXRT1166DVM6A MCU + + - 600MHz Cortex-M7 & 240Mhz Cortex-M4 + - 2MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4 + +- Memory + + - 512 Mbit SDRAM + - 128 Mbit QSPI Flash + - 512 Mbit Octal Flash + - TF socket for SD card + +- Display + + - MIPI LCD connector + +- Ethernet + + - 10/100 Mbit/s Ethernet PHY + - 10/100/1000 Mbit/s Ethernet PHY + +- USB + + - USB 2.0 OTG connector + - USB 2.0 host connector + +- Audio + + - 3.5 mm audio stereo headphone jack + - Board-mounted microphone + - Left and right speaker out connectors + +- Power + + - 5 V DC jack + +- Debug + + - JTAG 20-pin connector + - OpenSDA with DAPLink + +- Sensor + + - MIPI camera sensor connector + +- Expansion port + + - Arduino interface + +- CAN bus connector + +For more information about the MIMXRT1160 SoC and MIMXRT1160-EVK board, see +these references: + +- `i.MX RT1160 Website`_ +- `i.MX RT1160 Datasheet`_ +- `i.MX RT1160 Reference Manual`_ +- `MIMXRT1160-EVK Website`_ +- `MIMXRT1160-EVK Board Hardware User's Guide`_ + +Supported Features +================== + +The mimxrt1160_evk board configuration supports the following hardware +features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: +``boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig`` + +Other hardware features are not currently supported by the port. + +Connections and I/Os +==================== + +The MIMXRT1160 SoC has six pairs of pinmux/gpio controllers. + ++---------------+-----------------+---------------------------+ +| Name | Function | Usage | ++===============+=================+===========================+ +| WAKEUP | GPIO | SW7 | ++---------------+-----------------+---------------------------+ +| GPIO_AD_04 | GPIO | LED | ++---------------+-----------------+---------------------------+ +| GPIO_AD_24 | LPUART1_TX | UART Console | ++---------------+-----------------+---------------------------+ +| GPIO_AD_25 | LPUART1_RX | UART Console | ++---------------+-----------------+---------------------------+ + +System Clock +============ + +The MIMXRT1160 SoC is configured to use the 24 MHz external oscillator on the +board with the on-chip PLL to generate a 600 MHz core clock. + +Serial Port +=========== + +The MIMXRT1160 SoC has 12 UARTs. One is configured for the console and the +remaining are not used. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the :ref:`opensda-daplink-onboard-debug-probe`, +however the :ref:`pyocd-debug-host-tools` do not yet support programming the +external flashes on this board so you must reconfigure the board for one of the +following debug probes instead. + +:ref:`jlink-external-debug-probe` +--------------------------------- + +Install the :ref:`jlink-debug-host-tools` and make sure they are in your search +path. + +Attach a J-Link 20-pin connector to J1. Check that jumpers J6 and J7 +are **off** (they are on by default when boards ship from the factory) to +ensure SWD signals are disconnected from the OpenSDA microcontroller. + +Configuring a Console +===================== + +Regardless of your choice in debug probe, we will use the OpenSDA +microcontroller as a usb-to-serial adapter for the serial console. Check that +jumpers J5 and J8 are **on** (they are on by default when boards ship from +the factory) to connect UART signals to the OpenSDA microcontroller. + +Connect a USB cable from your PC to J11. + +Use the following settings with your serial terminal of choice (minicom, putty, +etc.): + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :ref:`hello_world` application. + +Before power on the board, make sure SW1 is set to 0001b + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk_cm7 + :goals: flash + +Power off the board, and change SW1 to 0010b. Then power on the board and +open a serial terminal, reset the board (press the SW4 button), and you should +see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.6.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk_cm7 + +Debugging +========= + +Here is an example for the :ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt1160_evk_cm7 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx ***** + Hello World! mimxrt1160_evk_cm7 + +.. _MIMXRT1160-EVK Website: + https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK + +.. _MIMXRT1160-EVK Board Hardware User's Guide: + https://www.nxp.com/docs/en/user-guide/UM11617.pdf + +.. _i.MX RT1160 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1160-crossover-mcu-family-high-performance-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1160 + +.. _i.MX RT1160 Datasheet: + https://www.nxp.com/docs/en/data-sheet/IMXRT1160CEC.pdf + +.. _i.MX RT1160 Reference Manual: + https://www.nxp.com/webapp/Download?colCode=IMXRT1160RM diff --git a/boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg b/boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg new file mode 100644 index 00000000000..7d86fb4e023 Binary files /dev/null and b/boards/arm/mimxrt1160_evk/doc/mimxrt1160_evk.jpg differ diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi b/boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi new file mode 100644 index 00000000000..1a6a46fc5e8 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk.dtsi @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + aliases { + led0 = &green_led; + sw0 = &user_button; + }; + + leds { + compatible = "gpio-leds"; + green_led: led-1 { + gpios = <&gpio9 3 GPIO_ACTIVE_LOW>; + label = "User LED D6"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button-1 { + label = "User SW7"; + gpios = <&gpio13 0 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&user_button { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts new file mode 100644 index 00000000000..d571b01cd1b --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.dts @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1160_evk.dtsi" + +/ { + model = "NXP MIMXRT1160-EVK board"; + compatible = "nxp,mimxrt1166"; + + chosen { + zephyr,sram = &sram1; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + }; + + + sdram0: memory@80000000 { + /* Winbond W9825G6KH-5I */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(64)>; + }; + +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml new file mode 100644 index 00000000000..dd2ded26718 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk_cm4 +name: NXP MIMXRT1160-EVK CM4 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 128 +flash: 128 +supported: + - gpio + - uart diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig new file mode 100644 index 00000000000..1b2d3608fde --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm4_defconfig @@ -0,0 +1,14 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SOC_MIMXRT1166_CM4=y +CONFIG_SOC_SERIES_IMX_RT=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts new file mode 100644 index 00000000000..004383e04f8 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.dts @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include "mimxrt1160_evk.dtsi" + +/ { + model = "NXP MIMXRT1160-EVK board"; + compatible = "nxp,mimxrt1166"; + + chosen { + zephyr,sram = &sdram0; + zephyr,dtcm = &dtcm; + zephyr,console = &lpuart1; + zephyr,shell-uart = &lpuart1; + zephyr,can-primary = &flexcan3; + }; + + sdram0: memory@80000000 { + /* Winbond W9825G6KH-5I */ + device_type = "memory"; + reg = <0x80000000 DT_SIZE_M(64)>; + }; +}; + +&lpuart1 { + status = "okay"; + current-speed = <115200>; +}; + +&flexspi1 { + reg = <0x400cc000 0x4000>, <0x30000000 DT_SIZE_M(16)>; + is25wp128: is25wp128@0 { + compatible = "issi,is25wp128"; + size = <134217728>; + label = "IS25WP128"; + reg = <0>; + spi-max-frequency = <133000000>; + status = "okay"; + jedec-id = [9d 70 17]; + }; +}; diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml new file mode 100644 index 00000000000..0e3f0262398 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7.yaml @@ -0,0 +1,19 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt1160_evk_cm7 +name: NXP MIMXRT1160-EVK CM7 +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 256 +flash: 16384 +supported: + - gpio + - counter diff --git a/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig new file mode 100644 index 00000000000..cdf79b282b8 --- /dev/null +++ b/boards/arm/mimxrt1160_evk/mimxrt1160_evk_cm7_defconfig @@ -0,0 +1,15 @@ +# +# Copyright (c) 2021, NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_SOC_MIMXRT1166_CM7=y +CONFIG_SOC_SERIES_IMX_RT=y +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_GPIO=y +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET=0x400 diff --git a/boards/arm/mimxrt1160_evk/pinmux.c b/boards/arm/mimxrt1160_evk/pinmux.c new file mode 100644 index 00000000000..6559031adba --- /dev/null +++ b/boards/arm/mimxrt1160_evk/pinmux.c @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include + +LOG_MODULE_REGISTER(mimxrt1160_evk, LOG_LEVEL_INF); + +static int mimxrt1160_evk_init(const struct device *dev) +{ + ARG_UNUSED(dev); + + CLOCK_EnableClock(kCLOCK_Iomuxc); + + /* Enable USER_LED_CTRL1 */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_04_GPIO9_IO03, 0U); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpuart1), okay) && CONFIG_SERIAL + /* LPUART1 TX/RX */ + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_24_LPUART1_TXD, 0U); + IOMUXC_SetPinMux(IOMUXC_GPIO_AD_25_LPUART1_RXD, 0U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_24_LPUART1_TXD, 0x02U); + IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_25_LPUART1_RXD, 0x02U); +#endif + return 0; +} + +SYS_INIT(mimxrt1160_evk_init, PRE_KERNEL_1, 0); diff --git a/dts/arm/nxp/nxp_rt1160_cm4.dtsi b/dts/arm/nxp/nxp_rt1160_cm4.dtsi new file mode 100644 index 00000000000..069cdcc6316 --- /dev/null +++ b/dts/arm/nxp/nxp_rt1160_cm4.dtsi @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + /delete-node/ cpu@0; + }; + + /* + * SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected + * to the M4 core alone, hence this EDMA controller has been designated M4 only. + * GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are + * only accesssible to the M4. + * + * Refer to Chapter 3 of the Reference Manual + */ + soc { + sram0: memory@1ffe0000 { + compatible = "mmio-sram"; + reg = <0x1ffe0000 DT_SIZE_K(128)>; + }; + + sram1: memory@20000000 { + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(128)>; + }; + + /* + * M4 uses different addresses from the M7 core for GPIO2 and + * GPIO3, see pg. 1364 of RT1160 ref manual for example + */ + gpio2: gpio@40130000 { + compatible = "nxp,imx-gpio"; + reg = <0x40130000 0x4000>; + interrupts = <102 0>, <103 0>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@40134000 { + compatible = "nxp,imx-gpio"; + reg = <0x40134000 0x4000>; + interrupts = <104 0>, <105 0>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; + + edma1: dma-controller@40c14000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma"; + dma-channels = <32>; + dma-requests = <128>; + nxp,mem2mem; + nxp,a_on; + reg = <0x40c14000 0x4000>, + <0x400c1800 0x4000>; + clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>; + status = "disabled"; + label = "EDMA1"; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>, + <16 0>; + }; + + }; + +}; + + +&gpio9 { + interrupts = <99 0>; +}; + +&gpio11 { + /* GPIO 7-11 share the same interrupt on the CM4 */ + interrupts = <99 0>; + status = "disabled"; +}; diff --git a/dts/arm/nxp/nxp_rt1160_cm7.dtsi b/dts/arm/nxp/nxp_rt1160_cm7.dtsi new file mode 100644 index 00000000000..0979c01f265 --- /dev/null +++ b/dts/arm/nxp/nxp_rt1160_cm7.dtsi @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2021, NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + cpus { + /delete-node/ cpu@1; + }; + /* + * ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected + * to the M7 core alone, hence this EDMA controller has been designated M7 only. + * GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is + * only accesssible to the M7. + * + * Refer to Chapter 3 of the Reference Manual + */ + soc { + flexram: flexram@40028000 { + reg = <0x40028000 0x4000>; + interrupts = <50 0>; + + #address-cells = <1>; + #size-cells = <1>; + + itcm: itcm@0 { + compatible = "nxp,imx-itcm"; + reg = <0x00000000 DT_SIZE_K(256)>; + }; + + dtcm: dtcm@20000000 { + compatible = "nxp,imx-dtcm"; + reg = <0x20000000 DT_SIZE_K(256)>; + }; + }; + + /* + * M7 uses different addresses from the M4 core for GPIO2 and + * GPIO3, see pg. 1460 of RT1160 ref manual for example + */ + gpio2: gpio@42008000 { + compatible = "nxp,imx-gpio"; + reg = <0x42008000 0x4000>; + interrupts = <102 0>, <103 0>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@4200c000 { + compatible = "nxp,imx-gpio"; + reg = <0x4200c000 0x4000>; + interrupts = <104 0>, <105 0>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; + + edma0: dma-controller@40070000 { + #dma-cells = <2>; + compatible = "nxp,mcux-edma"; + dma-channels = <32>; + dma-requests = <128>; + nxp,mem2mem; + nxp,a_on; + reg = <0x40070000 0x4000>, + <0x40074000 0x4000>; + clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>; + status = "disabled"; + label = "EDMA0"; + interrupts = <0 0>, <1 0>, <2 0>, <3 0>, + <4 0>, <5 0>, <6 0>, <7 0>, + <8 0>, <9 0>, <10 0>, <11 0>, + <12 0>, <13 0>, <14 0>, <15 0>, + <16 0>; + }; + }; +}; + +&gpio6 { + interrupts = <61 0>, <62 0>; +}; diff --git a/dts/arm/nxp/nxp_rt1170_cm4.dtsi b/dts/arm/nxp/nxp_rt1170_cm4.dtsi index d147f7a5ce3..655725dd0aa 100644 --- a/dts/arm/nxp/nxp_rt1170_cm4.dtsi +++ b/dts/arm/nxp/nxp_rt1170_cm4.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include / { cpus { @@ -30,6 +30,28 @@ reg = <0x20000000 DT_SIZE_K(128)>; }; + /* + * M4 uses different addresses from the M7 core for GPIO2 and + * GPIO3, see pg. 1410 of RT1170 ref manual for example + */ + gpio2: gpio@40130000 { + compatible = "nxp,imx-gpio"; + reg = <0x40130000 0x4000>; + interrupts = <102 0>, <103 0>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@40134000 { + compatible = "nxp,imx-gpio"; + reg = <0x40134000 0x4000>; + interrupts = <104 0>, <105 0>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; + edma1: dma-controller@40c14000 { #dma-cells = <2>; compatible = "nxp,mcux-edma"; diff --git a/dts/arm/nxp/nxp_rt1170_cm7.dtsi b/dts/arm/nxp/nxp_rt1170_cm7.dtsi index ffb6752b4fe..c235bba12e6 100644 --- a/dts/arm/nxp/nxp_rt1170_cm7.dtsi +++ b/dts/arm/nxp/nxp_rt1170_cm7.dtsi @@ -4,7 +4,7 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include +#include / { cpus { @@ -37,6 +37,28 @@ }; }; + /* + * M7 uses different addresses from the M4 core for GPIO2 and + * GPIO3, see pg. 1460 of RT1170 ref manual for example + */ + gpio2: gpio@42008000 { + compatible = "nxp,imx-gpio"; + reg = <0x42008000 0x4000>; + interrupts = <102 0>, <103 0>; + label = "GPIO_2"; + gpio-controller; + #gpio-cells = <2>; + }; + + gpio3: gpio@4200c000 { + compatible = "nxp,imx-gpio"; + reg = <0x4200c000 0x4000>; + interrupts = <104 0>, <105 0>; + label = "GPIO_3"; + gpio-controller; + #gpio-cells = <2>; + }; + edma0: dma-controller@40070000 { #dma-cells = <2>; compatible = "nxp,mcux-edma"; diff --git a/dts/arm/nxp/nxp_rt117x.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi similarity index 97% rename from dts/arm/nxp/nxp_rt117x.dtsi rename to dts/arm/nxp/nxp_rt11xx.dtsi index 810c3b5bd33..4d22eaf3946 100644 --- a/dts/arm/nxp/nxp_rt117x.dtsi +++ b/dts/arm/nxp/nxp_rt11xx.dtsi @@ -144,23 +144,11 @@ #gpio-cells = <2>; }; - gpio2: gpio@40130000 { - compatible = "nxp,imx-gpio"; - reg = <0x40130000 0x4000>; - interrupts = <102 0>, <103 0>; - label = "GPIO_2"; - gpio-controller; - #gpio-cells = <2>; - }; - - gpio3: gpio@40134000 { - compatible = "nxp,imx-gpio"; - reg = <0x40134000 0x4000>; - interrupts = <104 0>, <105 0>; - label = "GPIO_3"; - gpio-controller; - #gpio-cells = <2>; - }; + /* + * Note that CM7 and CM4 cores do not have the same memory addresses + * for GPIO2 and GPIO3, so those periperals are defined in the SOC + * specific DTS files + */ gpio4: gpio@40138000 { compatible = "nxp,imx-gpio"; diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 new file mode 100644 index 00000000000..ec984d6a9a3 --- /dev/null +++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm4 @@ -0,0 +1,17 @@ +# i.MX RT1160 CM4 + +# Copyright (c) 2021, NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT1166_CM4 + +config SOC + default "mimxrt1166_cm4" + +config NUM_IRQS + default 218 + +config GPIO + default y + +endif # SOC_MIMXRT1166_CM4 diff --git a/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 new file mode 100644 index 00000000000..a1739308c59 --- /dev/null +++ b/soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1166_cm7 @@ -0,0 +1,17 @@ +# i.MX RT1160 CM7 + +# Copyright (c) 2021, NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT1166_CM7 + +config SOC + default "mimxrt1166_cm7" + +config NUM_IRQS + default 218 + +config GPIO + default y + +endif # SOC_MIMXRT1166_CM7 diff --git a/soc/arm/nxp_imx/rt/Kconfig.soc b/soc/arm/nxp_imx/rt/Kconfig.soc index 8045b8556fe..54f3812f789 100644 --- a/soc/arm/nxp_imx/rt/Kconfig.soc +++ b/soc/arm/nxp_imx/rt/Kconfig.soc @@ -307,6 +307,52 @@ config SOC_MIMXRT1176_CM4 select INIT_VIDEO_PLL select HAS_MCUX_EDMA +config SOC_MIMXRT1166_CM7 + bool "SOC_MIMXRT1166_CM7" + select CPU_CORTEX_M7 + select CPU_CORTEX_M_HAS_DWT + select SOC_SERIES_IMX_RT11XX + select HAS_MCUX_CACHE + select HAS_MCUX + select HAS_MCUX_SEMC + select HAS_MCUX_CCM_REV2 + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPADC + select HAS_MCUX_LPUART + select HAS_MCUX_GPT + select HAS_MCUX_FLEXCAN + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_ENET_PLL if NET_L2_ETHERNET + select INIT_VIDEO_PLL + select HAS_MCUX_EDMA + select CPU_HAS_FPU_DOUBLE_PRECISION + select ADJUST_DCDC + select BYPASS_LDO_LPSR + select ADJUST_LDO + + +config SOC_MIMXRT1166_CM4 + bool "SOC_MIMXRT1166_CM4" + select CPU_CORTEX_M4 + select SOC_SERIES_IMX_RT11XX + select HAS_MCUX_CACHE + select HAS_MCUX + select HAS_MCUX_SEMC + select HAS_MCUX_CCM_REV2 + select HAS_MCUX_IGPIO + select HAS_MCUX_LPI2C + select HAS_MCUX_LPSPI + select HAS_MCUX_LPUART + select HAS_MCUX_GPT + select CPU_HAS_ARM_MPU + select INIT_ARM_PLL + select INIT_ENET_PLL if NET_L2_ETHERNET + select INIT_VIDEO_PLL + select HAS_MCUX_EDMA + endchoice if SOC_SERIES_IMX_RT @@ -386,6 +432,9 @@ config SOC_PART_NUMBER_MIMXRT1064CVL5A config SOC_PART_NUMBER_MIMXRT1064DVL6A bool +config SOC_PART_NUMBER_MIMXRT1166DVM6A + bool + config SOC_PART_NUMBER_MIMXRT1176AVM8A bool @@ -455,6 +504,7 @@ config SOC_PART_NUMBER_IMX_RT default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA + default "MIMXRT1166DVM6A" if SOC_PART_NUMBER_MIMXRT1166DVM6A default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA diff --git a/soc/arm/nxp_imx/rt/flexspi_nor_config.h b/soc/arm/nxp_imx/rt/flexspi_nor_config.h index 46e49b96125..2a0eb895aaf 100644 --- a/soc/arm/nxp_imx/rt/flexspi_nor_config.h +++ b/soc/arm/nxp_imx/rt/flexspi_nor_config.h @@ -135,21 +135,33 @@ enum { /* For flexspi_mem_config.controllerMiscOption */ enum { + /* !< Bit for Differential clock enable */ kFlexSpiMiscOffset_DiffClkEnable = 0, + /* !< Bit for CK2 enable */ kFlexSpiMiscOffset_Ck2Enable = 1, + /* !< Bit for Parallel mode enable */ kFlexSpiMiscOffset_ParallelEnable = 2, + /* !< Bit for Word Addressable enable */ kFlexSpiMiscOffset_WordAddressableEnable = 3, + /* !< Bit for Safe Configuration Frequency enable */ kFlexSpiMiscOffset_SafeConfigFreqEnable = 4, + /* !< Bit for Pad setting override enable */ kFlexSpiMiscOffset_PadSettingOverrideEnable = 5, + /* !< Bit for DDR clock configuration indication. */ kFlexSpiMiscOffset_DdrModeEnable = 6, }; /* For flexspi_mem_config.deviceType */ enum { + /* !< Flash devices are Serial NOR */ kFlexSpiDeviceType_SerialNOR = 1, + /* !< Flash devices are Serial NAND */ kFlexSpiDeviceType_SerialNAND = 2, + /* !< Flash devices are Serial RAM/HyperFLASH */ kFlexSpiDeviceType_SerialRAM = 3, + /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial NAND */ kFlexSpiDeviceType_MCP_NOR_NAND = 0x12, + /* !< Flash device is MCP device, A1 is Serial NOR, A2 is Serial RAMs */ kFlexSpiDeviceType_MCP_NOR_RAM = 0x13, }; @@ -162,11 +174,17 @@ enum { }; enum { + /* !< Generic command, for example: configure dummy cycles, drive strength, etc */ kDeviceConfigCmdType_Generic, + /* !< Quad Enable command */ kDeviceConfigCmdType_QuadEnable, + /* !< Switch from SPI to DPI/QPI/OPI mode */ kDeviceConfigCmdType_Spi2Xpi, + /* !< Switch from DPI/QPI/OPI to SPI mode */ kDeviceConfigCmdType_Xpi2Spi, + /* !< Switch to 0-4-4/0-8-8 mode */ kDeviceConfigCmdType_Spi2NoCmd, + /* !< Reset device command */ kDeviceConfigCmdType_Reset, }; @@ -177,53 +195,97 @@ struct flexspi_lut_seq_t { }; struct flexspi_mem_config_t { + /* !< [0x000-0x003] Tag, fixed value 0x42464346UL */ uint32_t tag; + /* !< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ uint32_t version; + /* !< [0x008-0x00b] Reserved for future use */ uint32_t reserved0; + /* !< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ uint8_t readSampleClkSrc; + /* !< [0x00d-0x00d] CS hold time, default value: 3 */ uint8_t csHoldTime; + /* !< [0x00e-0x00e] CS setup time, default value: 3 */ uint8_t csSetupTime; + /* !< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For */ uint8_t columnAddressWidth; - + /* ! Serial NAND, need to refer to datasheet */ + /* !< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ uint8_t deviceModeCfgEnable; + /* !< [0x011-0x011] Specify the configuration command + * type:Quad Enable, DPI/QPI/OPI switch, + */ uint8_t deviceModeType; - + /* ! Generic configuration, etc. */ + /* !< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for */ uint16_t waitTimeCfgCommands; - + /* ! DPI/QPI/OPI switch or reset command */ + /* !< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt */ struct flexspi_lut_seq_t deviceModeSeq; - + /* ! sequence number, [31:16] Reserved */ + /* !< [0x018-0x01b] Argument/Parameter for device configuration */ uint32_t deviceModeArg; + /* !< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ uint8_t configCmdEnable; + /* !< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ uint8_t configModeType[3]; + /* !< [0x020-0x02b] Sequence info for Device Configuration command, similar as + * deviceModeSeq + */ struct flexspi_lut_seq_t configCmdSeqs[3]; + /* !< [0x02c-0x02f] Reserved for future use */ uint32_t reserved1; + /* !< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ uint32_t configCmdArgs[3]; + /* !< [0x03c-0x03f] Reserved for future use */ uint32_t reserved2; + /* !< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more */ uint32_t controllerMiscOption; - + /* ! details */ + /* !< [0x044-0x044] Device Type: See Flash Type Definition for more details */ uint8_t deviceType; + /* !< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ uint8_t sflashPadType; + /* !< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot */ uint8_t serialClkFreq; - + /* ! Chapter for more details */ + /* !< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot */ uint8_t lutCustomSeqEnable; - + /* ! be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ + /* !< [0x048-0x04f] Reserved for future use */ uint32_t reserved3[2]; + /* !< [0x050-0x053] Size of Flash connected to A1 */ uint32_t sflashA1Size; + /* !< [0x054-0x057] Size of Flash connected to A2 */ uint32_t sflashA2Size; + /* !< [0x058-0x05b] Size of Flash connected to B1 */ uint32_t sflashB1Size; + /* !< [0x05c-0x05f] Size of Flash connected to B2 */ uint32_t sflashB2Size; + /* !< [0x060-0x063] CS pad setting override value */ uint32_t csPadSettingOverride; + /* !< [0x064-0x067] SCK pad setting override value */ uint32_t sclkPadSettingOverride; + /* !< [0x068-0x06b] data pad setting override value */ uint32_t dataPadSettingOverride; + /* !< [0x06c-0x06f] DQS pad setting override value */ uint32_t dqsPadSettingOverride; + /* !< [0x070-0x073] Timeout threshold for read status command */ uint32_t timeoutInMs; + /* !< [0x074-0x077] CS deselect interval between two commands */ uint32_t commandInterval; + /* !< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B, in terms of 0.1ns */ uint16_t dataValidTime[2]; + /* !< [0x07c-0x07d] Busy offset, valid value: 0-31 */ uint16_t busyOffset; + /* !< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - */ uint16_t busyBitPolarity; - + /* ! busy flag is 0 when flash device is busy */ + /* !< [0x080-0x17f] Lookup table holds Flash command sequences */ uint32_t lookupTable[64]; + /* !< [0x180-0x1af] Customizable LUT Sequences */ struct flexspi_lut_seq_t lutCustomSeq[12]; + /* !< [0x1b0-0x1bf] Reserved for future use */ uint32_t reserved4[4]; }; @@ -250,17 +312,29 @@ struct flexspi_mem_config_t { #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD 15 struct flexspi_nor_config_t { + /* !< Common memory configuration info via FlexSPI */ struct flexspi_mem_config_t memConfig; + /* !< Page size of Serial NOR */ uint32_t pageSize; + /* !< Sector size of Serial NOR */ uint32_t sectorSize; + /* !< Clock frequency for IP command */ uint8_t ipcmdSerialClkFreq; + /* !< Sector/Block size is the same */ uint8_t isUniformBlockSize; + /* !< Reserved for future use */ uint8_t reserved0[2]; + /* !< Serial NOR Flash type: 0/1/2/3 */ uint8_t serialNorType; + /* !< Need to exit NoCmd mode before other IP command */ uint8_t needExitNoCmdMode; + /* !< Half the Serial Clock for non-read command: true/false */ uint8_t halfClkForNonReadCmd; + /* !< Need to Restore NoCmd mode after IP commmand execution */ uint8_t needRestoreNoCmdMode; + /* !< Block size */ uint32_t blockSize; + /* !< Reserved for future use */ uint32_t reserve2[11]; }; diff --git a/soc/arm/nxp_imx/rt/soc_rt11xx.c b/soc/arm/nxp_imx/rt/soc_rt11xx.c index ca7ed11fcf9..78552aad727 100644 --- a/soc/arm/nxp_imx/rt/soc_rt11xx.c +++ b/soc/arm/nxp_imx/rt/soc_rt11xx.c @@ -30,10 +30,21 @@ #ifdef CONFIG_INIT_ARM_PLL static const clock_arm_pll_config_t armPllConfig = { +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) + /* resulting frequency: 24 * (166/(2* 2)) = 984MHz */ /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ .postDivider = kCLOCK_PllPostDiv2, /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ .loopDivider = 166, +#elif defined(CONFIG_SOC_MIMXRT1166_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM7) + /* resulting frequency: 24 * (200/(2 * 4)) = 600MHz */ + /* Post divider, 0 - DIV by 2, 1 - DIV by 4, 2 - DIV by 8, 3 - DIV by 1 */ + .postDivider = kCLOCK_PllPostDiv4, + /* PLL Loop divider, Fout = Fin * ( loopDivider / ( 2 * postDivider ) ) */ + .loopDivider = 200, +#else + #error "Unknown SOC, no pll configuration defined" +#endif }; #endif @@ -123,12 +134,15 @@ static ALWAYS_INLINE void clock_init(void) DCDC_SetVDD1P0BuckModeTargetVoltage(DCDC, kDCDC_1P0BuckTarget1P15V); #endif +/* RT1160 does not have Foward Body Biasing on the CM7 core */ +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1176_CM7) /* Check if FBB need to be enabled in OverDrive(OD) mode */ if (((OCOTP->FUSEN[7].FUSE & 0x10U) >> 4U) != 1) { PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, true); } else { PMU_EnableBodyBias(ANADIG_PMU, kPMU_FBB_CM7, false); } +#endif #if CONFIG_BYPASS_LDO_LPSR PMU_StaticEnableLpsrAnaLdoBypassMode(ANADIG_LDO_SNVS, true); @@ -181,17 +195,26 @@ static ALWAYS_INLINE void clock_init(void) (ANADIG_OSC->OSC_24M_CTRL & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)) { } + rootCfg.div = 1; + +#ifdef CONFIG_CPU_CORTEX_M7 /* Switch both core, M7 Systick and Bus_Lpsr to OscRC48MDiv2 first */ rootCfg.mux = kCLOCK_M7_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; - -#if CONFIG_SOC_MIMXRT1176_CM7 CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); + + rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); #endif -#if CONFIG_SOC_MIMXRT1176_CM4 +#if CONFIG_CPU_CORTEX_M4 + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); + + rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxOscRc48MDiv2; + rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); #endif @@ -252,28 +275,33 @@ static ALWAYS_INLINE void clock_init(void) /* Module clock root configurations. */ /* Configure M7 using ARM_PLL_CLK */ -#ifdef CONFIG_SOC_MIMXRT1176_CM7 +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) rootCfg.mux = kCLOCK_M7_ClockRoot_MuxArmPllOut; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M7, &rootCfg); #endif - /* Configure M4 using SYS_PLL3_PFD3_CLK */ -#ifdef CONFIG_SOC_MIMXRT1176_CM4 +#if defined(CONFIG_SOC_MIMXRT1166_CM4) + /* Configure M4 using SYS_PLL3_CLK */ + rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Out; + rootCfg.div = 2; + CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); +#elif defined(CONFIG_SOC_MIMXRT1176_CM4) + /* Configure M4 using SYS_PLL3_CLK_PFD3_CLK */ rootCfg.mux = kCLOCK_M4_ClockRoot_MuxSysPll3Pfd3; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4, &rootCfg); #endif /* Configure BUS using SYS_PLL3_CLK */ -#ifdef CONFIG_SOC_MIMXRT1176_CM7 +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) rootCfg.mux = kCLOCK_BUS_ClockRoot_MuxSysPll3Out; rootCfg.div = 2; CLOCK_SetRootClock(kCLOCK_Root_Bus, &rootCfg); #endif /* Configure BUS_LPSR using SYS_PLL3_CLK */ -#ifdef CONFIG_SOC_MIMXRT1176_CM4 +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) rootCfg.mux = kCLOCK_BUS_LPSR_ClockRoot_MuxSysPll3Out; rootCfg.div = 3; CLOCK_SetRootClock(kCLOCK_Root_Bus_Lpsr, &rootCfg); @@ -290,14 +318,14 @@ static ALWAYS_INLINE void clock_init(void) CLOCK_SetRootClock(kCLOCK_Root_Cstrace, &rootCfg); /* Configure M4_SYSTICK using OSC_RC_48M_DIV2 */ -#ifdef CONFIG_SOC_MIMXRT1176_CM4 +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) rootCfg.mux = kCLOCK_M4_SYSTICK_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 1; CLOCK_SetRootClock(kCLOCK_Root_M4_Systick, &rootCfg); #endif /* Configure M7_SYSTICK using OSC_RC_48M_DIV2 */ -#ifdef CONFIG_SOC_MIMXRT1176_CM7 +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) rootCfg.mux = kCLOCK_M7_SYSTICK_ClockRoot_MuxOscRc48MDiv2; rootCfg.div = 240; CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg); @@ -389,7 +417,7 @@ static int imxrt_init(const struct device *arg) SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; } -#if CONFIG_SOC_MIMXRT1176_CM7 +#if defined(CONFIG_SOC_MIMXRT1176_CM7) || defined(CONFIG_SOC_MIMXRT1166_CM7) if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { SCB_EnableICache(); } @@ -398,7 +426,7 @@ static int imxrt_init(const struct device *arg) } #endif -#if CONFIG_SOC_MIMXRT1176_CM4 +#if defined(CONFIG_SOC_MIMXRT1176_CM4) || defined(CONFIG_SOC_MIMXRT1166_CM4) /* Initialize Cache */ /* Enable Code Bus Cache */ if (0U == (LMEM->PCCCR & LMEM_PCCCR_ENCACHE_MASK)) { diff --git a/west.yml b/west.yml index 4cb770aa8aa..7f4569853b3 100644 --- a/west.yml +++ b/west.yml @@ -98,7 +98,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 2b3396864d2c60512038446f487c6dade6da6e04 + revision: fd8b79c40172e8aab808a3957978d49f46b01d87 path: modules/hal/nxp groups: - hal