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soc: stm32wl: enable instruction and data cache

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Enable instruction and data cache using the corresponding HAL functions.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit is contained in:
Fabio Baltieri 2021-06-25 22:07:34 +01:00 • committed by Anas Nashif
commit c08f3751bd
1 changed files with 5 additions and 0 deletions
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5
soc/arm/st_stm32/stm32wl/soc.c
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@ -13,6 +13,7 @@
#include <init.h>
#include <arch/cpu.h>
#include <arch/arm/aarch32/cortex_m/cmsis.h>
#include <stm32wlxx_ll_system.h>
/**
* @brief Perform basic hardware initialization at boot.
@ -28,6 +29,10 @@ static int stm32wl_init(const struct device *arg)
ARG_UNUSED(arg);
/* Enable CPU data and instruction cache */
LL_FLASH_EnableInstCache();
LL_FLASH_EnableDataCache();
key = irq_lock();
/* Install default handler that simply resets the CPU