michaelh/zephyr
1
0
Fork 0
Code Releases Activity

Renaming include/nanokernel to include/arch

Browse source 
Renaming the directory include/nanokernel to be include/arch, which
better reflects the real nature of the directory and the contents
inside.

Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade
Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
This commit is contained in:
Dan Kalowsky 2015-05-28 10:56:47 -07:00 • committed by Anas Nashif
commit c02dd34277
180 changed files with 195 additions and 195 deletions
Download patch file Download diff file Expand all files Collapse all files

67
include/arch/arc/arch.h Normal file
View file

@ -0,0 +1,67 @@
/* arch.h - ARC specific nanokernel interface header */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This header contains the ARC specific nanokernel interface. It is
included by the nanokernel interface architecture-abstraction header
(nanokernel/cpu.h)
*/
#ifndef _ARC_ARCH__H_
#define _ARC_ARCH__H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include <nanokernel.h>
#include <cputype.h>
#endif
#ifdef CONFIG_CPU_ARCV2
#include <arch/arc/v2/init.h>
#include <arch/arc/v2/exc.h>
#include <arch/arc/v2/irq.h>
#include <arch/arc/v2/ffs.h>
#include <arch/arc/v2/error.h>
#include <arch/arc/v2/misc.h>
#include <arch/arc/v2/aux_regs.h>
#include <arch/arc/v2/arcv2_irq_unit.h>
#endif
#ifdef __cplusplus
}
#endif
#endif /* _ARC_ARCH__H_ */

69
include/arch/arc/arcprc.h Normal file
View file

@ -0,0 +1,69 @@
/* cpu.h - ARC specific definitions for cputype.h */
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This file is included by cputype.h when the VXMICRO_ARCH_arc macro is
defined, i.e. whenever a build for the ARC architecture is being performed.
This file shall only contain the CPU/compiler specific
definitions that are necessary to build the EMBEDDED kernel library.
*/
#ifndef _ARC_CPU__H_
#define _ARC_CPU__H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <toolchain.h>
#include <misc/util.h>
#include <drivers/system_timer.h> /* timer_driver() needed by kernel_main.c */
/* sizes */
#define OCTET_TO_SIZEOFUNIT(X) (X)
#define SIZEOFUNIT_TO_OCTET(X) (X)
/* arch-specific event numbers */
#define TICK_EVENT 0
#define k_memcpy memcpy
#define k_memset memset
#ifdef __cplusplus
}
#endif
#endif /* _ARC_CPU__H_ */

124
include/arch/arc/v2/arcv2_irq_unit.h Normal file
View file

@ -0,0 +1,124 @@
/* arcv2_irq_unit.h - ARCv2 Interrupt Unit device driver */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ARC_V2_IRQ_UNIT__H
#define _ARC_V2_IRQ_UNIT__H
/* configuration flags for interrupt unit */
#define _ARC_V2_INT_DISABLE 0
#define _ARC_V2_INT_ENABLE 1
#define _ARC_V2_INT_LEVEL 0
#define _ARC_V2_INT_PULSE 1
#ifndef _ASMLANGUAGE
/*
* WARNING:
*
* All APIs provided by this file must be invoked with INTERRUPTS LOCKED. The
* APIs themselves are writing the IRQ_SELECT, selecting which IRQ's registers
* it wants to write to, then write to them: THIS IS NOT AN ATOMIC OPERATION.
*
* Not locking the interrupts inside of the APIs allows a caller to:
*
* - lock interrupts
* - call many of these APIs
* - unlock interrupts
*
* thus being more efficient then if the APIs themselves would lock
* interrupts.
*/
/*
* _arc_v2_irq_unit_irq_enable_set - enable/disable interrupt
*
* Enables or disables the specified interrupt
*
* RETURNS: N/A
*/
static inline void _arc_v2_irq_unit_irq_enable_set(
int irq,
unsigned char enable
)
{
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_ENABLE, enable);
}
/*
* _arc_v2_irq_unit_int_enable - enable interrupt
*
* Enables the specified interrupt
*
* RETURNS: N/A
*/
static inline void _arc_v2_irq_unit_int_enable(int irq)
{
_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_ENABLE);
}
/*
* _arc_v2_irq_unit_int_disable - disable interrupt
*
* Disables the specified interrupt
*
* RETURNS: N/A
*/
static inline void _arc_v2_irq_unit_int_disable(int irq)
{
_arc_v2_irq_unit_irq_enable_set(irq, _ARC_V2_INT_DISABLE);
}
/*
* _arc_v2_irq_unit_prio_set - set interrupt priority
*
* Set the priority of the specified interrupt
*
* RETURNS: N/A
*/
static inline void _arc_v2_irq_unit_prio_set(int irq, unsigned char prio)
{
_arc_v2_aux_reg_write(_ARC_V2_IRQ_SELECT, irq);
_arc_v2_aux_reg_write(_ARC_V2_IRQ_PRIORITY, prio);
}
void _arc_v2_irq_unit_int_eoi(int irq);
void _arc_v2_irq_unit_init(void);
#endif /* _ASMLANGUAGE */
#endif /* _ARC_V2_IRQ_UNIT__H */

119
include/arch/arc/v2/aux_regs.h Normal file
View file

@ -0,0 +1,119 @@
/* aux_regs.h - ARCv2 auxiliary registers definitions */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Definitions for auxiliary registers.
*/
#ifndef _ARC_V2_AUX_REGS__H_
#define _ARC_V2_AUX_REGS__H_
#define _ARC_V2_LP_START 0x002
#define _ARC_V2_LP_END 0x003
#define _ARC_V2_STATUS32 0x00a
#define _ARC_V2_STATUS32_P0 0x00b
#define _ARC_V2_AUX_IRQ_CTRL 0x00e
#define _ARC_V2_IC_CTRL 0x011
#define _ARC_V2_TMR0_COUNT 0x021
#define _ARC_V2_TMR0_CONTROL 0x022
#define _ARC_V2_TMR0_LIMIT 0x023
#define _ARC_V2_AUX_IRQ_ACT 0x043
#define _ARC_V2_TMR1_COUNT 0x100
#define _ARC_V2_TMR1_CONTROL 0x101
#define _ARC_V2_TMR1_LIMIT 0x102
#define _ARC_V2_IRQ_PRIO_PEND 0x200
#define _ARC_V2_AUX_IRQ_HINT 0x201
#define _ARC_V2_IRQ_PRIORITY 0x206
#define _ARC_V2_ERET 0x400
#define _ARC_V2_ERSTATUS 0x402
#define _ARC_V2_ECR 0x403
#define _ARC_V2_EFA 0x404
#define _ARC_V2_ICAUSE 0x40a
#define _ARC_V2_IRQ_SELECT 0x40b
#define _ARC_V2_IRQ_ENABLE 0x40c
#define _ARC_V2_IRQ_TRIGGER 0x40d
#define _ARC_V2_IRQ_STATUS 0x40f
#define _ARC_V2_IRQ_PULSE_CANCEL 0x415
#define _ARC_V2_IRQ_PENDING 0x416
/* STATUS32/STATUS32_P0 bits */
#define _ARC_V2_STATUS32_H (1 << 0)
#define _ARC_V2_STATUS32_E(x) ((x) << 1)
#define _ARC_V2_STATUS32_AE_BIT 5
#define _ARC_V2_STATUS32_AE (1 << ARC_V2_STATUS32_AE_BIT)
#define _ARC_V2_STATUS32_DE (1 << 6)
#define _ARC_V2_STATUS32_U (1 << 7)
#define _ARC_V2_STATUS32_V (1 << 8)
#define _ARC_V2_STATUS32_C (1 << 9)
#define _ARC_V2_STATUS32_N (1 << 10)
#define _ARC_V2_STATUS32_Z (1 << 11)
#define _ARC_V2_STATUS32_L (1 << 12)
#define _ARC_V2_STATUS32_DZ (1 << 13)
#define _ARC_V2_STATUS32_SC (1 << 14)
#define _ARC_V2_STATUS32_ES (1 << 15)
#define _ARC_V2_STATUS32_RB(x) ((x) << 16)
#define _ARC_V2_STATUS32_IE (1 << 31)
/* exception cause register masks */
#define _ARC_V2_ECR_VECTOR(X) ((X & 0xff0000) >> 16)
#define _ARC_V2_ECR_CODE(X) ((X & 0xff00) >> 8)
#define _ARC_V2_ECR_PARAMETER(X) (X & 0xff)
#ifndef _ASMLANGUAGE
#if defined(__GNUC__)
#define _arc_v2_aux_reg_read(reg) __builtin_arc_lr(reg)
#define _arc_v2_aux_reg_write(reg, val) __builtin_arc_sr((unsigned int)val, reg)
#else /* ! __GNUC__ */
#define _arc_v2_aux_reg_read(reg) \
({ \
unsigned int __ret; \
__asm__ __volatile__(" lr 0, [%1]" \
: "=r"(__ret) \
: "i"(reg)); \
__ret; \
})
#define _arc_v2_aux_reg_write(reg, val) \
({ \
__asm__ __volatile__(" sr %0, [%1]" \
: \
: "ir"(val), "i"(reg)); \
})
#endif /* __GNUC__ */
#endif /* _ASMLANGUAGE */
#endif /* _ARC_V2_AUX_REGS__H_ */

54
include/arch/arc/v2/error.h Normal file
View file

@ -0,0 +1,54 @@
/* v2/error.h - ARCv2 public error handling */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARC-specific nanokernel error handling interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_ERROR_H_
#define _ARCH_ARC_V2_ERROR_H_
#include <arch/arc/v2/exc.h>
#ifndef _ASMLANGUAGE
extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int,
const NANO_ESF *);
extern void _SysFatalErrorHandler(unsigned int cause, const NANO_ESF *esf);
#endif
#define _NANO_ERR_HW_EXCEPTION (0) /* MPU/Bus/Usage fault */
#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
#define _NANO_ERR_STACK_CHK_FAIL (2) /* Stack corruption detected */
#define _NANO_ERR_INVALID_STRING_OP (3) /* Invalid string operation */
#endif /* _ARCH_ARC_V2_ERROR_H_ */

52
include/arch/arc/v2/exc.h Normal file
View file

@ -0,0 +1,52 @@
/* v2/exc.h - ARCv2 public exception handling */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARC-specific nanokernel exception handling interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_EXC_H_
#define _ARCH_ARC_V2_EXC_H_
#ifdef _ASMLANGUAGE
#else
struct __esf {
/* XXX - not defined yet */
int placeholder;
};
typedef struct __esf NANO_ESF;
extern const NANO_ESF _default_esf;
#endif
#endif /* _ARCH_ARC_V2_EXC_H_ */

109
include/arch/arc/v2/ffs.h Normal file
View file

@ -0,0 +1,109 @@
/* v2/ffs.h - ARCv2 public nanokernel find-first-set interface */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARC-specific nanokernel ffs interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_FFS_H_
#define _ARCH_ARC_V2_FFS_H_
#ifdef _ASMLANGUAGE
GTEXT(nanoFfsLsb);
GTEXT(nanoFfsMsb);
#else
extern unsigned nanoFfsLsb(unsigned int);
extern unsigned nanoFfsMsb(unsigned int);
/*******************************************************************************
*
* nanoFfsMsb_inline - Find First Set bit (searching from most significant bit)
*
* This routine finds the first bit set in the argument passed it and returns
* the index of that bit. Bits are numbered starting at 1 from the least
* significant bit. A return value of zero indicates that the value passed
* is zero.
*
* RETURNS: most significant bit set
*/
#if defined(__GNUC__)
static ALWAYS_INLINE unsigned int nanoFfsMsb_inline(unsigned int op)
{
unsigned int bit;
__asm__ volatile(
/* see explanation in ffs.s */
"fls.f %0, %1;\n\t"
"add.nz %0, %0, 1;\n\t"
: "=r"(bit)
: "r"(op));
return bit;
}
#endif
/*******************************************************************************
*
* nanoFfsLsb - find first set bit (searching from the least significant bit)
*
* This routine finds the first bit set in the argument passed it and
* returns the index of that bit. Bits are numbered starting
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
*/
#if defined(__GNUC__)
static ALWAYS_INLINE unsigned int nanoFfsLsb_inline(unsigned int op)
{
unsigned int bit;
__asm__ volatile(
/* see explanation in ffs.s */
"ffs.f %0, %1;\n\t"
"add.nz %0, %0, 1;\n\t"
"mov.z %0, 0;\n\t"
: "=&r"(bit)
: "r"(op));
return bit;
}
#endif
#endif /* _ASMLANGUAGE */
#endif /* _ARCH_ARC_V2_FFS_H_ */

45
include/arch/arc/v2/init.h Normal file
View file

@ -0,0 +1,45 @@
/* ARC/v2/init.h - ARCv2 public initialization */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* DESCRIPTION
* ARCv2-specific nanokernel initialization interface. Included by ARC/arch.h.
*/
#ifndef _ARCH_ARC_V2_INIT_H_
#define _ARCH_ARC_V2_INIT_H_
#ifndef _ASMLANGUAGE
extern void _nano_fiber_swap(void);
#endif
#endif /* _ARCH_ARC_V2_INIT_H_ */

111
include/arch/arc/v2/irq.h Normal file
View file

@ -0,0 +1,111 @@
/* arc/v2/irq.h - ARCv2 public interrupt handling */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
* DESCRIPTION
* ARCv2 nanokernel interrupt handling interface. Included by ARC/v2/arch.h.
*/
#ifndef _ARCH_ARC_V2_IRQ__H_
#define _ARCH_ARC_V2_IRQ__H_
#include <arch/arc/v2/aux_regs.h>
#ifdef _ASMLANGUAGE
GTEXT(_irq_exit);
GTEXT(irq_lock)
GTEXT(irq_unlock)
GTEXT(irq_handler_set)
GTEXT(irq_connect)
GTEXT(irq_disconnect)
GTEXT(irq_enable)
GTEXT(irq_disable)
GTEXT(irq_priority_set)
#else
extern int irq_lock(void);
extern void irq_unlock(int key);
extern void irq_handler_set(unsigned int irq,
void (*old)(void *arg),
void (*new)(void *arg),
void *arg);
extern int irq_connect(unsigned int irq,
unsigned int prio,
void (*isr)(void *arg),
void *arg);
extern void irq_disconnect(unsigned int irq);
extern void irq_enable(unsigned int irq);
extern void irq_disable(unsigned int irq);
extern void irq_priority_set(unsigned int irq, unsigned int prio);
extern void _irq_exit(void);
/*******************************************************************************
*
* irq_lock_inline - disable all interrupts on the CPU (inline)
*
* See irq_lock() for full description
*
* RETURNS: An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
*/
static ALWAYS_INLINE unsigned int irq_lock_inline(void)
{
unsigned int key;
__asm__ volatile("clri %0" : "=r"(key));
return key;
}
/*******************************************************************************
*
* irq_unlock_inline - enable all interrupts on the CPU (inline)
*
* See irq_unlock() for full description
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static ALWAYS_INLINE void irq_unlock_inline(unsigned int key)
{
__asm__ volatile("seti %0" : : "ir"(key));
}
#endif /* _ASMLANGUAGE */
#endif /* _ARCH_ARC_V2_IRQ__H_ */

47
include/arch/arc/v2/misc.h Normal file
View file

@ -0,0 +1,47 @@
/* CortexM/misc.h - Cortex-M public nanokernel miscellaneous */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARC-specific nanokernel miscellaneous interface. Included by arc/arch.h.
*/
#ifndef _ARCH_ARC_V2_MISC_H_
#define _ARCH_ARC_V2_MISC_H_
#ifndef _ASMLANGUAGE
extern unsigned int nano_cpu_sleep_mode;
extern void nano_cpu_idle(void);
extern void nano_cpu_atomic_idle(unsigned int key);
#endif
#endif /* _ARCH_ARC_V2_MISC_H_ */

65
include/arch/arm/ARMprc.h Normal file
View file

@ -0,0 +1,65 @@
/* cpu.h - ARM specific definitions for cputype.h */
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This file is included by cputype.h when the VXMICRO_ARCH_arm macro is
defined, i.e. whenever a build for the ARM architecture is being performed.
This file shall only contain the CPU/compiler specific
definitions that are necessary to build the EMBEDDED kernel library.
*/
#ifndef _ARM_CPU__H_
#define _ARM_CPU__H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <toolchain.h>
#include <misc/util.h>
#include <drivers/system_timer.h> /* timer_driver() needed by kernel_main.c */
/* sizes */
#define OCTET_TO_SIZEOFUNIT(X) (X)
#define SIZEOFUNIT_TO_OCTET(X) (X)
#define k_memcpy memcpy
#define k_memset memset
#ifdef __cplusplus
}
#endif
#endif /* _ARM_CPU__H_ */

47
include/arch/arm/CortexM/asm_inline.h Normal file
View file

@ -0,0 +1,47 @@
/* Intel ARM inline assembler functions and macros for public functions */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ASM_INLINE_PUBLIC_H
#define _ASM_INLINE_PUBLIC_H
/*
* The file must not be included directly
* Include nanokernel/cpu.h instead
*/
#if defined(__GNUC__)
#include <arch/arm/CortexM/asm_inline_gcc.h>
#else
#include <arch/arm/CortexM/asm_inline_other.h>
#endif
#endif /* _ASM_INLINE_PUBLIC_H */

181
include/arch/arm/CortexM/asm_inline_gcc.h Normal file
View file

@ -0,0 +1,181 @@
/* Intel ARM GCC specific public inline assembler functions and macros */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* Either public functions or macros or invoked by public functions */
#ifndef _ASM_INLINE_GCC_PUBLIC_GCC_H
#define _ASM_INLINE_GCC_PUBLIC_GCC_H
/*
* The file must not be included directly
* Include nanokernel/cpu.h instead
*/
#ifdef _ASMLANGUAGE
#define _SCS_BASE_ADDR _PPB_INT_SCS
#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
#define _SCS_ICSR_PENDSV (1 << 28)
#define _SCS_ICSR_UNPENDSV (1 << 27)
#define _SCS_ICSR_RETTOBASE (1 << 11)
#else /* !_ASMLANGUAGE */
#include <stdint.h>
#include <arch/arm/CortexM/nvic.h>
/*******************************************************************************
*
* find_last_set_inline - find first set bit (searching from most significant bit)
*
* This routine finds the first bit set in the argument passed it and returns
* the index of that bit. Bits are numbered starting at 1 from the least
* significant bit. A return value of zero indicates that the value passed
* is zero.
*
* RETURNS: most significant bit set
*/
static ALWAYS_INLINE unsigned int find_last_set_inline(unsigned int op)
{
unsigned int bit;
__asm__ volatile(
"cmp %1, #0;\n\t"
"itt ne;\n\t"
" clzne %1, %1;\n\t"
" rsbne %0, %1, #32;\n\t"
: "=r"(bit)
: "r"(op));
return bit;
}
/*******************************************************************************
*
* find_first_set_inline - find first set bit (from the least significant bit)
*
* This routine finds the first bit set in the argument passed it and
* returns the index of that bit. Bits are numbered starting
* at 1 from the least significant bit. A return value of zero indicates that
* the value passed is zero.
*
* RETURNS: least significant bit set
*/
static ALWAYS_INLINE unsigned int find_first_set_inline(unsigned int op)
{
unsigned int bit;
__asm__ volatile(
"rsb %0, %1, #0;\n\t"
"ands %0, %0, %1;\n\t" /* r0 = x & (-x): only LSB set */
"itt ne;\n\t"
" clzne %0, %0;\n\t" /* count leading zeroes */
" rsbne %0, %0, #32;\n\t"
: "=&r"(bit)
: "r"(op));
return bit;
}
/*******************************************************************************
*
* irq_lock_inline - disable all interrupts on the CPU (inline)
*
* This routine disables interrupts. It can be called from either interrupt,
* task or fiber level. This routine returns an architecture-dependent
* lock-out key representing the "interrupt disable state" prior to the call;
* this key can be passed to irq_unlock_inline() to re-enable interrupts.
*
* The lock-out key should only be used as the argument to the
* irq_unlock_inline() API. It should never be used to manually re-enable
* interrupts or to inspect or manipulate the contents of the source register.
*
* WARNINGS
* Invoking a VxMicro routine with interrupts locked may result in
* interrupts being re-enabled for an unspecified period of time. If the
* called routine blocks, interrupts will be re-enabled while another
* context executes, or while the system is idle.
*
* The "interrupt disable state" is an attribute of a context. Thus, if a
* fiber or task disables interrupts and subsequently invokes a VxMicro
* system routine that causes the calling context to block, the interrupt
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
*/
static ALWAYS_INLINE unsigned int irq_lock_inline(void)
{
unsigned int key;
__asm__ volatile(
"movs.n %%r1, %1;\n\t"
"mrs %0, BASEPRI;\n\t"
"msr BASEPRI, %%r1;\n\t"
: "=r"(key)
: "i"(_EXC_IRQ_DEFAULT_PRIO)
: "r1");
return key;
}
/*******************************************************************************
*
* irq_unlock_inline - enable all interrupts on the CPU (inline)
*
* This routine re-enables interrupts on the CPU. The <key> parameter
* is an architecture-dependent lock-out key that is returned by a previous
* invocation of irq_lock_inline().
*
* This routine can be called from either interrupt, task or fiber level.
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static ALWAYS_INLINE void irq_unlock_inline(unsigned int key)
{
__asm__ volatile("msr BASEPRI, %0;\n\t" : : "r"(key));
}
#endif /* _ASMLANGUAGE */
#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */

54
include/arch/arm/CortexM/error.h Normal file
View file

@ -0,0 +1,54 @@
/* CortexM/error.h - Cortex-M public error handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel error handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_ERROR_H_
#define _ARCH_ARM_CORTEXM_ERROR_H_
#include <arch/arm/CortexM/exc.h>
#ifndef _ASMLANGUAGE
extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int,
const NANO_ESF *);
extern void _SysFatalErrorHandler(unsigned int, const NANO_ESF *);
#endif
#define _NANO_ERR_HW_EXCEPTION (0) /* MPU/Bus/Usage fault */
#define _NANO_ERR_INVALID_TASK_EXIT (1) /* Invalid task exit */
#define _NANO_ERR_STACK_CHK_FAIL (2) /* Stack corruption detected */
#define _NANO_ERR_INVALID_STRING_OP (3) /* Invalid string operation */
#endif /* _ARCH_ARM_CORTEXM_ERROR_H_ */

62
include/arch/arm/CortexM/exc.h Normal file
View file

@ -0,0 +1,62 @@
/* CortexM/exc.h - Cortex-M public exception handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel exception handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_EXC_H_
#define _ARCH_ARM_CORTEXM_EXC_H_
#ifdef _ASMLANGUAGE
GTEXT(_ExcExit);
#else
struct __esf {
uint32_t a1; /* r0 */
uint32_t a2; /* r1 */
uint32_t a3; /* r2 */
uint32_t a4; /* r3 */
uint32_t ip; /* r12 */
uint32_t lr; /* r14 */
uint32_t pc; /* r15 */
uint32_t xpsr;
};
typedef struct __esf NANO_ESF;
extern const NANO_ESF _default_esf;
extern void _ExcExit(void);
#endif
#endif /* _ARCH_ARM_CORTEXM_EXC_H_ */

50
include/arch/arm/CortexM/ffs.h Normal file
View file

@ -0,0 +1,50 @@
/* CortexM/ffs.h - Cortex-M public nanokernel find-first-set interface */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel ffs interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_FFS_H_
#define _ARCH_ARM_CORTEXM_FFS_H_
#ifdef _ASMLANGUAGE
GTEXT(find_first_set);
GTEXT(find_last_set);
#else
extern unsigned find_first_set(unsigned int);
extern unsigned find_last_set(unsigned int);
#endif /* _ASMLANGUAGE */
#endif /* _ARCH_ARM_CORTEXM_FFS_H_ */

75
include/arch/arm/CortexM/gdb_stub.h Normal file
View file

@ -0,0 +1,75 @@
/* gdb_stub.s - extra work performed upon exception entry/exit for GDB */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Prep work done when entering exceptions consists of saving the callee-saved
registers before they get used by exception handlers, and recording the fact
that we are running in an exception.
*/
#ifndef _GDB_STUB__H_
#define _GDB_STUB__H_
#ifdef _ASMLANGUAGE
#if CONFIG_GDB_INFO
GTEXT(_GdbStubExcEntry)
_GDB_STUB_EXC_ENTRY: .macro
push {lr}
bl irq_lock
bl _GdbStubExcEntry
bl irq_unlock
pop {lr}
.endm
GTEXT(_GdbStubExcExit)
_GDB_STUB_EXC_EXIT: .macro
push {lr}
bl irq_lock
bl _GdbStubExcExit
bl irq_unlock
pop {lr}
.endm
GTEXT(_irq_vector_table_entry_with_gdb_stub)
#else
#define _GDB_STUB_EXC_ENTRY
#define _GDB_STUB_EXC_EXIT
#endif /* CONFIG_GDB_INFO */
#else
extern void _irq_vector_table_entry_with_gdb_stub(void);
#endif /* _ASMLANGUAGE */
#endif /* _GDB_STUB__H_ */

45
include/arch/arm/CortexM/init.h Normal file
View file

@ -0,0 +1,45 @@
/* CortexM/init.h - Cortex-M public initialization */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel initialization interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_INIT_H_
#define _ARCH_ARM_CORTEXM_INIT_H_
#ifndef _ASMLANGUAGE
extern void _nano_fiber_swap(void);
#endif
#endif /* _ARCH_ARM_CORTEXM_INIT_H_ */

76
include/arch/arm/CortexM/irq.h Normal file
View file

@ -0,0 +1,76 @@
/* CortexM/irq.h - Cortex-M public interrupt handling */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel interrupt handling interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_IRQ_H_
#define _ARCH_ARM_CORTEXM_IRQ_H_
#include <arch/arm/CortexM/nvic.h>
#ifdef _ASMLANGUAGE
GTEXT(_IntExit);
GTEXT(irq_lock)
GTEXT(irq_unlock)
GTEXT(irq_handler_set)
GTEXT(irq_connect)
GTEXT(irq_disconnect)
GTEXT(irq_enable)
GTEXT(irq_disable)
GTEXT(irq_priority_set)
#else
extern int irq_lock(void);
extern void irq_unlock(int key);
extern void irq_handler_set(unsigned int irq,
void (*old)(void *arg),
void (*new)(void *arg),
void *arg);
extern int irq_connect(unsigned int irq,
unsigned int prio,
void (*isr)(void *arg),
void *arg);
extern void irq_disconnect(unsigned int irq);
extern void irq_enable(unsigned int irq);
extern void irq_disable(unsigned int irq);
extern void irq_priority_set(unsigned int irq, unsigned int prio);
extern void _IntExit(void);
#endif /* _ASMLANGUAGE */
#endif /* _ARCH_ARM_CORTEXM_IRQ_H_ */

53
include/arch/arm/CortexM/memory_map-m0.h Normal file
View file

@ -0,0 +1,53 @@
/* memory_map-m0.h - ARM CORTEX-M0 memory map */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This module contains definitions for the memory map parts specific to the
CORTEX-M0 series of processors. It is included by nanokernel/ARM/memory_map.h
*/
#ifndef _MEMORY_MAP_M0__H_
#define _MEMORY_MAP_M0__H_
/* 0xe0000000 -> 0xe00fffff: private peripheral bus [1MB] */
#define _PPB_INT_BASE_ADDR (_EDEV_END_ADDR + 1)
#define _PPB_INT_SCS (_PPB_INT_BASE_ADDR + KB(56))
#define _PPB_INT_END_ADDR (_PPB_INT_BASE_ADDR + MB(1) - 1)
/* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB] */
#define _SYSTEM_BASE_ADDR (_PPB_INT_END_ADDR + 1)
#define _SYSTEM_END_ADDR 0xffffffff
#endif /* _MEMORY_MAP_M0__H_ */

67
include/arch/arm/CortexM/memory_map-m3.h Normal file
View file

@ -0,0 +1,67 @@
/* memory_map-m3.h - ARM CORTEX-M3 memory map */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This module contains definitions for the memory map parts specific to the
CORTEX-M3 series of processors. It is included by nanokernel/ARM/memory_map.h
*/
#ifndef _MEMORY_MAP_M3__H_
#define _MEMORY_MAP_M3__H_
/* 0xe0000000 -> 0xe00fffff: private peripheral bus */
/* 0xe0000000 -> 0xe003ffff: internal [256KB] */
#define _PPB_INT_BASE_ADDR (_EDEV_END_ADDR + 1)
#define _PPB_INT_ITM _PPB_INT_BASE_ADDR
#define _PPB_INT_DWT (_PPB_INT_ITM + KB(4))
#define _PPB_INT_FPB (_PPB_INT_DWT + KB(4))
#define _PPB_INT_RSVD_1 (_PPB_INT_FPB + KB(4))
#define _PPB_INT_SCS (_PPB_INT_RSVD_1 + KB(44))
#define _PPB_INT_RSVD_2 (_PPB_INT_SCS + KB(4))
#define _PPB_INT_END_ADDR (_PPB_INT_RSVD_2 + KB(196) - 1)
/* 0xe0040000 -> 0xe00fffff: external [768K] */
#define _PPB_EXT_BASE_ADDR (_PPB_INT_END_ADDR + 1)
#define _PPB_EXT_TPIU _PPB_EXT_BASE_ADDR
#define _PPB_EXT_ETM (_PPB_EXT_TPIU + KB(4))
#define _PPB_EXT_PPB (_PPB_EXT_ETM + KB(4))
#define _PPB_EXT_ROM_TABLE (_PPB_EXT_PPB + KB(756))
#define _PPB_EXT_END_ADDR (_PPB_EXT_ROM_TABLE + KB(4) - 1)
/* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB] */
#define _VENDOR_BASE_ADDR (_PPB_EXT_END_ADDR + 1)
#define _VENDOR_END_ADDR 0xffffffff
#endif /* _MEMORY_MAP_M3__H_ */

83
include/arch/arm/CortexM/memory_map.h Normal file
View file

@ -0,0 +1,83 @@
/* memory_map.h - ARM CORTEX-M memory map */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This module contains definitions for the memory map of the CORTEX-M series of
processors.
*/
#ifndef _CORTEXM_MEMORY_MAP__H_
#define _CORTEXM_MEMORY_MAP__H_
#include <misc/util.h>
/* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
#define _CODE_BASE_ADDR 0
#define _CODE_END_ADDR (_CODE_BASE_ADDR + MB(512) - 1)
/* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
#define _SRAM_BASE_ADDR (_CODE_END_ADDR + 1)
#define _SRAM_BIT_BAND_REGION (_SRAM_BASE_ADDR)
#define _SRAM_BIT_BAND_REGION_END (_SRAM_BIT_BAND_REGION + MB(1) - 1)
#define _SRAM_BIT_BAND_ALIAS (_SRAM_BIT_BAND_REGION + MB(32))
#define _SRAM_BIT_BAND_ALIAS_END (_SRAM_BIT_BAND_ALIAS + MB(32) - 1)
#define _SRAM_END_ADDR (_SRAM_BASE_ADDR + MB(512) - 1)
/* 0x40000000 -> 0x5fffffff: Peripherals [0.5GB] */
#define _PERI_BASE_ADDR (_SRAM_END_ADDR + 1)
#define _PERI_BIT_BAND_REGION (_PERI_BASE_ADDR)
#define _PERI_BIT_BAND_REGION_END (_PERI_BIT_BAND_REGION + MB(1) - 1)
#define _PERI_BIT_BAND_ALIAS (_PERI_BIT_BAND_REGION + MB(32))
#define _PERI_BIT_BAND_ALIAS_END (_PERI_BIT_BAND_ALIAS + MB(32) - 1)
#define _PERI_END_ADDR (_PERI_BASE_ADDR + MB(512) - 1)
/* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
#define _ERAM_BASE_ADDR (_PERI_END_ADDR + 1)
#define _ERAM_END_ADDR (_ERAM_BASE_ADDR + GB(1) - 1)
/* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
#define _EDEV_BASE_ADDR (_ERAM_END_ADDR + 1)
#define _EDEV_END_ADDR (_EDEV_BASE_ADDR + GB(1) - 1)
/* 0xe0000000 -> 0xffffffff is different between M3 and M0 */
#if defined(CONFIG_CPU_CORTEXM3)
#include <arch/arm/CortexM/memory_map-m3.h>
#elif defined(CONFIG_CPU_CORTEXM0)
#include <arch/arm/CortexM/memory_map-m0.h>
#else
#error Unknown CPU
#endif
#endif /* _CORTEXM_MEMORY_MAP__H_ */

45
include/arch/arm/CortexM/misc.h Normal file
View file

@ -0,0 +1,45 @@
/* CortexM/misc.h - Cortex-M public nanokernel miscellaneous */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
ARM-specific nanokernel miscellaneous interface. Included by ARM/arch.h.
*/
#ifndef _ARCH_ARM_CORTEXM_MISC_H_
#define _ARCH_ARM_CORTEXM_MISC_H_
#ifndef _ASMLANGUAGE
extern void nano_cpu_idle(void);
#endif
#endif /* _ARCH_ARM_CORTEXM_MISC_H_ */

237
include/arch/arm/CortexM/nvic.h Normal file
View file

@ -0,0 +1,237 @@
/* nvic.c - ARM CORTEX-M Series Nested Vector Interrupt Controller */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Provide an interface to the Nested Vectored Interrupt Controller found on
ARM Cortex-M processors.
The API does not account for all possible usages of the NVIC, only the
functionalities needed by the VxMicro kernel.
The same effect can be achieved by directly writing in the registers of the
NVIC, with the layout available from scs.h, using the __scs.nvic data
structure (or hardcoded values), but these APIs are less error-prone,
especially for registers with multiple instances to account for potentially
240 interrupt lines. If access to a missing functionality is needed, this is
the way to implement it.
Supports up to 240 IRQs and 256 priority levels.
*/
#ifndef _NVIC_H_
#define _NVIC_H_
#include <misc/__assert.h>
#include <arch/arm/CortexM/scs.h>
/* for assembler, only works with constants */
#define _EXC_PRIO(pri) (((pri) << (8 - CONFIG_NUM_IRQ_PRIO_BITS)) & 0xff)
#if defined(CONFIG_ZERO_LATENCY_IRQS)
#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(0x03)
#else
#define _EXC_IRQ_DEFAULT_PRIO _EXC_PRIO(0x02)
#endif
/* no exc #0 */
#define _EXC_RESET 1
#define _EXC_NMI 2
#define _EXC_HARD_FAULT 3
#define _EXC_MPU_FAULT 4
#define _EXC_BUS_FAULT 5
#define _EXC_USAGE_FAULT 6
/* 7-10 reserved */
#define _EXC_SVC 11
#define _EXC_DEBUG 12
/* 13 reserved */
#define _EXC_PENDSV 14
#define _EXC_SYSTICK 15
/* 16+ IRQs */
#define NUM_IRQS_PER_REG 32
#define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
#define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
#if !defined(_ASMLANGUAGE)
#include <stdint.h>
/*******************************************************************************
*
* _NvicIrqEnable - enable an IRQ
*
* Enable IRQ #<irq>, which is equivalent to exception #<irq>+16
*
* RETURNS: N/A
*/
static inline void _NvicIrqEnable(unsigned int irq /* IRQ number */
)
{
__scs.nvic.iser[REG_FROM_IRQ(irq)] = 1 << BIT_FROM_IRQ(irq);
}
/*******************************************************************************
*
* _NvicIsIrqEnabled - find out if an IRQ is enabled
*
* Find out if IRQ #<irq> is enabled.
*
* RETURNS: 1 if IRQ is enabled, 0 otherwise
*/
static inline int _NvicIsIrqEnabled(unsigned int irq /* IRQ number */
)
{
return __scs.nvic.iser[REG_FROM_IRQ(irq)] & (1 << BIT_FROM_IRQ(irq));
}
/*******************************************************************************
*
* _NvicIrqEnable - disable an IRQ
*
* Disable IRQ #<irq>, which is equivalent to exception #<irq>+16
*
* RETURNS: N/A
*/
static inline void _NvicIrqDisable(unsigned int irq /* IRQ number */
)
{
__scs.nvic.icer[REG_FROM_IRQ(irq)] = 1 << BIT_FROM_IRQ(irq);
}
/*******************************************************************************
*
* _NvicIrqPend - pend an IRQ
*
* Pend IRQ #<irq>, which is equivalent to exception #<irq>+16. CPU will handle
* the IRQ when interrupts are enabled and/or returning from a higher priority
* interrupt.
*
* RETURNS: N/A
*/
static inline void _NvicIrqPend(unsigned int irq /* IRQ number */
)
{
__scs.nvic.ispr[REG_FROM_IRQ(irq)] = 1 << BIT_FROM_IRQ(irq);
}
/*******************************************************************************
*
* _NvicIsIrqPending - find out if an IRQ is pending
*
* Find out if IRQ #<irq> is pending
*
* RETURNS: 1 if IRQ is pending, 0 otherwise
*/
static inline int _NvicIsIrqPending(unsigned int irq /* IRQ number */
)
{
return __scs.nvic.ispr[REG_FROM_IRQ(irq)] & (1 << BIT_FROM_IRQ(irq));
}
/*******************************************************************************
*
* _NvicIrqUnpend - unpend an IRQ
*
* Unpend IRQ #<irq>, which is equivalent to exception #<irq>+16. The previously
* pending interrupt will be ignored when either unlocking interrupts or
* returning from a higher priority exception.
*
* RETURNS: N/A
*/
static inline void _NvicIrqUnpend(unsigned int irq /* IRQ number */
)
{
__scs.nvic.icpr[REG_FROM_IRQ(irq)] = 1 << BIT_FROM_IRQ(irq);
}
/*******************************************************************************
*
* _NvicIrqPrioSet - set priority of an IRQ
*
* Set priority of IRQ #<irq> to <prio>. There are 256 priority levels.
*
* RETURNS: N/A
*/
static inline void _NvicIrqPrioSet(unsigned int irq, /* IRQ number */
unsigned int prio /* priority */
)
{
__ASSERT(prio < 256, "invalid priority\n");
__scs.nvic.ipr[irq] = prio;
}
/*******************************************************************************
*
* _NvicIrqPrioGet - get priority of an IRQ
*
* Get priority of IRQ #<irq>.
*
* RETURNS: the priority level of the IRQ
*/
static inline uint32_t _NvicIrqPrioGet(unsigned int irq /* IRQ number */
)
{
return __scs.nvic.ipr[irq];
}
/*******************************************************************************
*
* _NvicSwInterruptTrigger - trigger an interrupt via software
*
* Trigger interrupt #<irq>. The CPU will handle the IRQ when interrupts are
* enabled and/or returning from a higher priority interrupt.
*
* RETURNS: N/A
*/
static inline void _NvicSwInterruptTrigger(unsigned int irq /* IRQ number */
)
{
#if defined(CONFIG_BSP_TI_LM3S6965_QEMU)
/* the QEMU does not simulate the STIR register: this is a workaround */
_NvicIrqPend(irq);
#else
__scs.stir = irq;
#endif
}
#endif /* !_ASMLANGUAGE */
#endif /* _NVIC_H_ */

1232
include/arch/arm/CortexM/scb.h Normal file
View file

File diff suppressed because it is too large Load diff

232
include/arch/arm/CortexM/scripts/linker.cmd Normal file
View file

@ -0,0 +1,232 @@
/* linker.cmd - Linker command/script file */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Linker script for the Cortex-M3 BSPs.
*/
#define _LINKER
#define _ASMLANGUAGE
#include <autoconf.h>
#include <sections.h>
#include <linker-tool.h>
/* physical address of RAM */
#ifdef CONFIG_XIP
#define ROMABLE_REGION FLASH
#define RAMABLE_REGION SRAM
#elif CONFIG_BOOTLOADER
#define ROMABLE_REGION SRAM
#define RAMABLE_REGION SRAM
#else
/* default Qemu model */
#define ROMABLE_REGION FLASH
#define RAMABLE_REGION SRAM
#endif
#if defined(CONFIG_XIP)
#define _DATA_IN_ROM __data_rom_start
#else
#define _DATA_IN_ROM
#endif
#if !defined(SKIP_TO_SECURITY_FRDM_K64F)
#define SKIP_TO_SECURITY_FRDM_K64F
#endif
MEMORY
{
FLASH (rx) : ORIGIN = FLASH_START, LENGTH = FLASH_SIZE
SRAM (wx) : ORIGIN = SRAM_START, LENGTH = SRAM_SIZE
SYSTEM_CONTROL_SPACE (wx) : ORIGIN = 0xE000E000, LENGTH = 4K
SYSTEM_CONTROL_PERIPH (wx) : ORIGIN = 0x400FE000, LENGTH = 4K
}
SECTIONS
{
GROUP_START(ROMABLE_REGION)
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{
KEEP(*(.exc_vector_table))
KEEP(*(".exc_vector_table.*"))
#if defined(CONFIG_GDB_INFO) && !defined(CONFIG_SW_ISR_TABLE)
KEEP(*(.gdb_stub_irq_vector_table))
KEEP(*(".gdb_stub_irq_vector_table.*"))
#endif
KEEP(*(.irq_vector_table))
KEEP(*(".irq_vector_table.*"))
/* FRDM_K64F has to write 16 bytes at 0x400 */
SKIP_TO_SECURITY_FRDM_K64F
KEEP(*(.security_frdm_k64f))
KEEP(*(".security_frdm_k64f.*"))
*(.text)
*(".text.*")
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(.ARM.exidx,,)
{
/*
* This section, related to stack and exception unwinding, is placed
* explicitly to prevent it from being shared between multiple regions.
* It must be defined for gcc to support 64-bit math and avoid
* section overlap.
*/
__exidx_start = .;
#if defined (__GCC_LINKER_CMD__)
*(.ARM.exidx* gnu.linkonce.armexidx.*)
#endif
__exidx_end = .;
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_CTOR_SECTION_NAME,,)
{
/*
* The compiler fills the constructor pointers table below, hence symbol
* __CTOR_LIST__ must be aligned on 4 byte boundary.
* To align with the C++ standard, the first element of the array
* contains the number of actual constructors. The last element is
* NULL.
*/
. = ALIGN(4);
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".ctors*")))
LONG(0)
__CTOR_END__ = .;
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{
*(.rodata)
*(".rodata.*")
} GROUP_LINK_IN(ROMABLE_REGION)
__data_rom_start = ALIGN(4); /* XIP imaged DATA ROM start addr */
GROUP_END(ROMABLE_REGION)
GROUP_START(RAMABLE_REGION)
#if defined(CONFIG_XIP)
SECTION_AT_PROLOGUE(_DATA_SECTION_NAME,,,_DATA_IN_ROM)
#else
SECTION_PROLOGUE(_DATA_SECTION_NAME,,)
#endif
{
__data_ram_start = .;
*(.data)
*(".data.*")
} GROUP_LINK_IN(RAMABLE_REGION)
__data_ram_end = .;
SECTION_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
{
/*
* For performance, BSS section is assumed to be 4 byte aligned and
* a multiple of 4 bytes
*/
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(".bss.*")
COMMON_SYMBOLS
/*
* BSP clears this memory in words only and doesn't clear any
* potential left over bytes.
*/
__bss_end = ALIGN(4);
} GROUP_LINK_IN(RAMABLE_REGION)
SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
{
/*
* This section is used for non-intialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
} GROUP_LINK_IN(RAMABLE_REGION)
/* Define linker symbols */
_end = .; /* end of image */
__bss_num_words = (__bss_end - __bss_start) >> 2;
GROUP_END(RAMABLE_REGION)
GROUP_START(SYSTEM_CONTROL_PERIPH)
SECTION_PROLOGUE(.scp,(NOLOAD),)
{
/*
* The leading '.' in the ".scp" section name indicates that section is
* mapped to neither a normal ROM nor a normal RAM area.
*/
*(.scp)
*(".scp.*")
} GROUP_LINK_IN(SYSTEM_CONTROL_PERIPH)
GROUP_END(SYSTEM_CONTROL_PERIPH)
GROUP_START(SYSTEM_CONTROL_SPACE)
SECTION_PROLOGUE(.scs,(NOLOAD),)
{
/*
* The leading '.' in the ".scs" section name indicates that section is
* mapped to neither normal ROM nor normal RAM space.
*/
*(.scs)
*(".scs.*")
} GROUP_LINK_IN(SYSTEM_CONTROL_SPACE)
GROUP_END(SYSTEM_CONTROL_SPACE)
}
#ifdef CONFIG_XIP
/*
* Round up number of words for DATA section to ensure that XIP copies the
* entire data section. XIP copy is done in words only, so there may be up
* to 3 extra bytes copied in next section (BSS). At run time, the XIP copy
* is done first followed by clearing the BSS section.
*/
__data_size = (__data_ram_end - __data_ram_start);
__data_num_words = (__data_size + 3) >> 2;
#endif

547
include/arch/arm/CortexM/scs.h Normal file
View file

@ -0,0 +1,547 @@
/* scs.h - ARM CORTEX-M System Control Space */
/*
* Copyright (c) 2013-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Define the System Control Space for the CORTEX-M series of processors and
provide an interface for miscellaneous SCS functionalities.
All register and bit-field names come from the
Cortex-M3 Devices
Generic User Guide
ARM DUI 0552A (ID121610)
and
Cortex-M3
Revision r2p1
Technical Reference Manual
ARM DDI 0337I (ID072410)
documents from ARM.
The API does not account for all possible usages of the SCS, only the
functionalities needed by the VxMicro kernel. It does not contain NVIC and
SCB functionalities either: these can be found in nvic.h and scb.h.
MPU functionalities are not implemented.
The same effect can be achieved by directly writing in the registers of the
SCS, using the __scs data structure (or hardcoded values), but the APIs found
here are less error-prone, especially for registers with multiple instances to
account for 16 exceptions.
If access to a missing functionality is needed, directly writing to the
registers is the way to implement it.
Note that the 'stir' register, even if not in the 'nvic' part of the SCB, is
still considered part of the NVIC and an API for it is provided in nvic.h.
*/
#ifndef _SCS__H_
#define _SCS__H_
#ifdef _ASMLANGUAGE
#include <arch/arm/CortexM/memory_map.h>
#else /* _ASMLANGUAGE */
#include <nanokernel.h>
#include <arch/cpu.h>
#include <stdint.h>
union __ictr {
uint32_t val;
struct {
uint32_t intlinesnum : 4 __attribute__((packed));
uint32_t rsvd__4_31 : 28 __attribute__((packed));
} bit;
};
union __actlr {
uint32_t val;
struct {
uint32_t dismcycint : 1 __attribute__((packed));
uint32_t disdefwbuf : 1 __attribute__((packed));
uint32_t disfold : 1 __attribute__((packed));
uint32_t rsvd__3_31 : 28 __attribute__((packed));
} bit;
};
union __stcsr {
uint32_t val;
struct {
uint8_t enable : 1 __attribute__((packed));
uint8_t tickint : 1 __attribute__((packed));
uint8_t clksource : 1 __attribute__((packed));
uint16_t rsvd__3_15 : 13 __attribute__((packed));
uint16_t countflag : 1 __attribute__((packed));
uint16_t rsvd__17_31 : 15 __attribute__((packed));
} bit;
};
union __cpuid {
uint32_t val;
struct {
uint32_t revision : 4 __attribute__((packed));
uint32_t partno : 12 __attribute__((packed));
uint32_t constant : 4 __attribute__((packed));
uint32_t variant : 4 __attribute__((packed));
uint32_t implementer : 8 __attribute__((packed));
} bit;
};
union __icsr {
uint32_t val;
struct {
uint32_t vectactive : 9 __attribute__((packed));
uint32_t rsvd__9_10 : 2 __attribute__((packed));
uint32_t rettobase : 1 __attribute__((packed));
uint32_t vectpending : 10 __attribute__((packed));
uint32_t isrpending : 1 __attribute__((packed));
uint32_t rsvd__23 : 1 __attribute__((packed));
uint32_t rsvd__24 : 1 __attribute__((packed));
uint32_t pendstclr : 1 __attribute__((packed));
uint32_t pendstset : 1 __attribute__((packed));
uint32_t pendsvclr : 1 __attribute__((packed));
uint32_t pendsvset : 1 __attribute__((packed));
uint32_t rsvd__29_30 : 2 __attribute__((packed));
uint32_t nmipendset : 1 __attribute__((packed));
} bit;
};
union __vtor {
uint32_t val;
struct {
uint32_t rsvd__0_6 : 7 __attribute__((packed));
uint32_t tbloff : 22 __attribute__((packed));
uint32_t tblbase : 1 __attribute__((packed));
uint32_t rsvd__30_31 : 2 __attribute__((packed));
} bit;
};
union __aircr {
uint32_t val;
struct {
uint32_t vecreset : 1 __attribute__((packed)); /* WO */
uint32_t vectclractive : 1 __attribute__((packed)); /* WO */
uint32_t sysresetreq : 1 __attribute__((packed)); /* WO */
uint32_t rsvd__3_7 : 5 __attribute__((packed));
uint32_t prigroup : 3 __attribute__((packed));
uint32_t rsvd__11_14 : 4 __attribute__((packed));
uint32_t endianness : 1 __attribute__((packed)); /* RO */
uint32_t vectkey : 16 __attribute__((packed));
} bit;
};
union __scr {
uint32_t val;
struct {
uint32_t rsvd__0 : 1 __attribute__((packed));
uint32_t sleeponexit : 1 __attribute__((packed));
uint32_t sleepdeep : 1 __attribute__((packed));
uint32_t rsvd__3 : 1 __attribute__((packed));
uint32_t sevonpend : 1 __attribute__((packed));
uint32_t rsvd__5_31 : 27 __attribute__((packed));
} bit;
};
#define _SCB_CCR_DIV_0_TRP (1 << 4)
#define _SCB_CCR_UNALIGN_TRP (1 << 3)
union __ccr {
uint32_t val;
struct {
uint32_t nonbasethrdena : 1 __attribute__((packed));
uint32_t usersetmpend : 1 __attribute__((packed));
uint32_t rsvd__2 : 1 __attribute__((packed));
uint32_t unalign_trp : 1 __attribute__((packed));
uint32_t div_0_trp : 1 __attribute__((packed));
uint32_t rsvd__5_7 : 3 __attribute__((packed));
uint32_t bfhfnmign : 1 __attribute__((packed));
uint32_t stkalign : 1 __attribute__((packed));
uint32_t rsvd__10_31 : 22 __attribute__((packed));
} bit;
};
union __shcsr {
uint32_t val;
struct {
uint32_t memfaultact : 1 __attribute__((packed));
uint32_t busfaultact : 1 __attribute__((packed));
uint32_t rsvd__2 : 1 __attribute__((packed));
uint32_t usgfaultact : 1 __attribute__((packed));
uint32_t rsvd__4_6 : 3 __attribute__((packed));
uint32_t svcallact : 1 __attribute__((packed));
uint32_t monitoract : 1 __attribute__((packed));
uint32_t rsvd__9 : 1 __attribute__((packed));
uint32_t pendsvact : 1 __attribute__((packed));
uint32_t systickact : 1 __attribute__((packed));
uint32_t usgfaultpended : 1 __attribute__((packed));
uint32_t memfaultpended : 1 __attribute__((packed));
uint32_t busfaultpended : 1 __attribute__((packed));
uint32_t svcallpended : 1 __attribute__((packed));
uint32_t memfaultena : 1 __attribute__((packed));
uint32_t busfaultena : 1 __attribute__((packed));
uint32_t usgfaultena : 1 __attribute__((packed));
uint32_t rsvd__19_31 : 13 __attribute__((packed));
} bit;
};
union __cfsr {
uint32_t val;
struct {
union {
uint8_t val;
struct {
uint8_t iaccviol : 1 __attribute__((packed));
uint8_t daccviol : 1 __attribute__((packed));
uint8_t rsvd__2 : 1 __attribute__((packed));
uint8_t munstkerr : 1 __attribute__((packed));
uint8_t mstkerr : 1 __attribute__((packed));
uint8_t rsvd__5_6 : 2 __attribute__((packed));
uint8_t mmarvalid : 1 __attribute__((packed));
} bit;
} mmfsr;
union {
uint8_t val;
struct {
uint8_t ibuserr : 1 __attribute__((packed));
uint8_t preciserr : 1 __attribute__((packed));
uint8_t impreciserr : 1 __attribute__((packed));
uint8_t unstkerr : 1 __attribute__((packed));
uint8_t stkerr : 1 __attribute__((packed));
uint8_t rsvd__5_6 : 2 __attribute__((packed));
uint8_t bfarvalid : 1 __attribute__((packed));
} bit;
} bfsr;
union {
uint16_t val;
struct {
uint16_t undefinstr : 1 __attribute__((packed));
uint16_t invstate : 1 __attribute__((packed));
uint16_t invpc : 1 __attribute__((packed));
uint16_t nocp : 1 __attribute__((packed));
uint16_t rsvd__4_7 : 4 __attribute__((packed));
uint16_t unaligned : 1 __attribute__((packed));
uint16_t divbyzero : 1 __attribute__((packed));
uint16_t rsvd__10_15 : 6
__attribute__((packed));
} bit;
} ufsr;
} byte;
};
union __hfsr {
uint32_t val;
struct {
uint32_t rsvd__0 : 1 __attribute__((packed));
uint32_t vecttbl : 1 __attribute__((packed));
uint32_t rsvd__2_29 : 28 __attribute__((packed));
uint32_t forced : 1 __attribute__((packed));
uint32_t debugevt : 1 __attribute__((packed));
} bit;
};
union __mpu_type {
uint32_t val;
struct {
uint32_t separate : 1 __attribute__((packed));
uint32_t rsvd__1_7 : 7 __attribute__((packed));
uint32_t dregion : 8 __attribute__((packed));
uint32_t iregion : 8 __attribute__((packed));
uint32_t rsvd__24_31 : 8 __attribute__((packed));
} bit;
};
union __mpu_ctrl {
uint32_t val;
struct {
uint32_t enable : 1 __attribute__((packed));
uint32_t hfnmiena : 1 __attribute__((packed));
uint32_t privdefena : 1 __attribute__((packed));
uint32_t rsvd__24_31 : 29 __attribute__((packed));
} bit;
};
union __mpu_rnr {
uint32_t val;
struct {
uint32_t region : 8 __attribute__((packed));
uint32_t rsvd__24_31 : 24 __attribute__((packed));
} bit;
};
union __mpu_rbar {
uint32_t val;
struct {
uint8_t region : 4 __attribute__((packed));
uint8_t valid : 1 __attribute__((packed));
uint32_t addr : 27 __attribute__((packed));
} bit;
};
union __mpu_rasr {
uint32_t val;
struct {
uint32_t enable : 1 __attribute__((packed));
uint32_t size : 5 __attribute__((packed));
uint32_t rsvd__6_7 : 2 __attribute__((packed));
uint32_t srd : 8 __attribute__((packed));
uint32_t b : 1 __attribute__((packed));
uint32_t c : 1 __attribute__((packed));
uint32_t s : 1 __attribute__((packed));
uint32_t tex : 3 __attribute__((packed));
uint32_t rsvd__22_23 : 2 __attribute__((packed));
uint32_t ap : 3 __attribute__((packed));
uint32_t rsvd__27 : 1 __attribute__((packed));
uint32_t xn : 1 __attribute__((packed));
uint32_t rsvd__29_31 : 3 __attribute__((packed));
} bit;
};
struct __scs {
uint32_t rsvd__MasterControlRegister;
union __ictr ictr; /* 0x004 Interrupt Controller Type Register */
union __actlr actlr; /* 0x008 Auxiliary ConTroL Register */
uint32_t rsvd__00c_00f;
/* system ticker (SYSTICK) */
struct {
union __stcsr stcsr; /* 0x10 Control and Status Register */
uint32_t strvr; /* 0x14 Reload Value Register (low 24 bits) */
uint32_t stcvr; /* 0x18 Current Value Register (low 24 bits) */
uint32_t stcr; /* 0x1c Calibration value Register */
} systick; /* offset: 0x010, size 0x10 */
uint32_t rsvd__020_0ff[(0x100 - 0x20) / 4];
/* Nested Vector Interrupt Controller (NVIC)
*
* Each block of 8 32-bit words could in theory support 256 IRQs, but
* the architecture only supports IRQs 0 -> 239.
*/
struct {
uint32_t iser[8]; /* 0x100 Interrupt Set-Enable Registers */
uint32_t rsvd__120_17f[24];
uint32_t icer[8]; /* 0x180 Interrupt Clear-Enable Registers */
uint32_t rsvd__1a0_1ff[24];
uint32_t ispr[8]; /* 0x200 Interrupt Set-Pending Registers */
uint32_t rsvd__220_27f[24];
uint32_t icpr[8]; /* 0x280 Interrupt Clear-Pending Registers */
uint32_t rsvd__2a0_2ff[24];
uint32_t iabr[8]; /* 0x300 Interrupt Active-Bit Registers */
uint32_t rsvd__320_37f[24];
uint32_t rsvd__380_3ff[32];
uint8_t ipr[240]; /* 0x400 Interrupt Priority Registers */
uint32_t rsvd__4f0_4ff[4];
} nvic; /* offset: 0x100, size 0x400 */
uint32_t rsvd__500_cff[(0xd00 - 0x500) / 4];
/* System Control Block (SCB) */
struct {
union __cpuid cpuid; /* 0xd00 CPUID register */
union __icsr icsr; /* 0xd04 IRQ Control and Start Register */
union __vtor vtor; /* 0xd08 Vector Table Offset Register */
union __aircr
aircr; /* 0xd0c App IRQ and Reset Control Register */
union __scr scr; /* 0xd10 System Control Register */
union __ccr ccr; /* 0xd14 Configuration and Control Register */
uint8_t shpr[12]; /* 0xd18 System Handler Priority Registers
Use ('exception number' - 4) to
get index into array */
union __shcsr
shcsr; /* 0xd24 Sys Handler Control and State Reg */
union __cfsr cfsr; /* 0xd28 Configurable Fault Status Register
*/
union __hfsr hfsr; /* 0xd2C Hard Fault Status Register */
uint32_t dfsr; /* 0xd30 Debug Fault Status Register */
uint32_t mmfar; /* 0xd34 MemManage Fault Address Register */
uint32_t bfar; /* 0xd38 BusFault Address Register */
uint32_t afsr; /* 0xd3C Aux Fault Status Register */
} scb; /* offset: 0xd00, size 0x040 */
/* d40 -> d7f: processor feature ID registers (pp.778-779 in DDI0403D)
*/
uint32_t rsvd__d40_d8f[(0xd90 - 0xd40) / 4];
/* Memory Protection Unit (MPU) */
struct { /* 0xD90-0xDA3 */
union __mpu_type mpu_type; /* 0xd90 RO TYPE register */
union __mpu_ctrl mpu_ctrl; /* 0xd94 RW ConTRoL register */
union __mpu_rnr mpu_rnr; /* 0xd98 RW Region Number Register */
union __mpu_rbar mpu_rbar; /* 0xd9c RW Region Base Addr Reg. */
union __mpu_rasr mpu_rasr; /* 0xda0 RW Region Attr and Size
Reg.*/
union __mpu_rbar mpu_rbar_a1; /* 0xda4 RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a1; /* 0xda8 RW alias of mpu_rasr */
union __mpu_rbar mpu_rbar_a2; /* 0xdac RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a2; /* 0xdb0 RW alias of mpu_rasr */
union __mpu_rbar mpu_rbar_a3; /* 0xdb4 RW alias of mpu_rbar */
union __mpu_rasr mpu_rasr_a3; /* 0xdb8 RW alias of mpu_rasr */
} mpu; /* offset: 0xd90, size: 0x02c */
uint32_t rsvd__da4_eff[(0xf00 - 0xdbc) / 4];
uint32_t
stir; /* 0xf00 WO SW Trigger IRQ Reg. (bit 0-8/IRQ 0-239 only)
*/
uint32_t rsvd__f04_fff[(0x1000 - 0xF04) / 4];
};
/* the linker always puts this object at 0xe000e000 */
extern volatile struct __scs __scs;
/* API */
/*******************************************************************************
*
* _ScsNumIrqGet - obtain the number of interrupt lines on the target
*
* RETURNS: the number of interrupts
*/
static inline int _ScsNumIrqGet(void)
{
return 32 * (__scs.ictr.bit.intlinesnum + 1);
}
/*******************************************************************************
*
* _ScsIntMultiCycleInstDisable - disable load/store multiple instructions
*
* From the ARM manuals:
*
* LDM/STM instructions increase the interrupt latency of the processor because
* they must complete before the processor can stack the current state and invoke
* the interrupt handler.
*
* RETURNS: N/A
*/
static inline void _ScsIntMultiCycleInstDisable(void)
{
__scs.actlr.bit.dismcycint = 1;
}
/*******************************************************************************
*
* _ScsIntMultiCycleInstEnable - enable load/store multiple instructions
*
* See _ScsIntMultiCycleInstDisable().
*
* RETURNS: N/A
*/
static inline void _ScsIntMultiCycleInstEnable(void)
{
__scs.actlr.bit.dismcycint = 0;
}
/*******************************************************************************
*
* _ScsWriteBufDisable - disable write buffer
*
* From the ARM manuals:
*
* Disables write buffer use during default memory map accesses. This causes all
* BusFaults to be precise BusFaults but decreases performance because any store
* to memory must complete before the processor can execute the next instruction.
*
* RETURNS: N/A
*/
static inline void _ScsWriteBufDisable(void)
{
__scs.actlr.bit.disdefwbuf = 1;
}
/*******************************************************************************
*
* _ScsWriteBufEnable - enable write buffer
*
* See _ScsWriteBufDisable().
*
* RETURNS: N/A
*/
static inline void _ScsWriteBufEnable(void)
{
__scs.actlr.bit.disdefwbuf = 0;
}
/*******************************************************************************
*
* _ScsFoldItDisable - disable IT folding
*
* From the ARM manuals:
*
* In some situations, the processor can start executing the first instruction
* in an IT block while it is still executing the IT instruction. This behavior
* is called IT folding, and improves performance, However, IT folding can cause
* jitter in looping. If a task must avoid jitter, set the DISFOLD bit to 1
* before executing the task, to disable IT folding.
*
* RETURNS: N/A
*/
static inline void _ScsFoldItDisable(void)
{
__scs.actlr.bit.disfold = 1;
}
/*******************************************************************************
*
* _ScsFoldItEnable - enable IT folding
*
* See _ScsFoldItDisable().
*
* RETURNS: N/A
*/
static inline void _ScsFoldItEnable(void)
{
__scs.actlr.bit.disfold = 0;
}
#endif /* _ASMLANGUAGE */
#endif /* _SCS__H_ */

71
include/arch/arm/arch.h Normal file
View file

@ -0,0 +1,71 @@
/* arch.h - ARM specific nanokernel interface header */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This header contains the ARM specific nanokernel interface. It is
included by the nanokernel interface architecture-abstraction header
(nanokernel/cpu.h)
*/
#ifndef _ARM_ARCH__H_
#define _ARM_ARCH__H_
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include <nanokernel.h>
#include <cputype.h>
#endif
#ifdef CONFIG_CPU_CORTEXM
#include <arch/arm/CortexM/init.h>
#include <arch/arm/CortexM/exc.h>
#include <arch/arm/CortexM/irq.h>
#include <arch/arm/CortexM/ffs.h>
#include <arch/arm/CortexM/error.h>
#include <arch/arm/CortexM/misc.h>
#include <arch/arm/CortexM/scs.h>
#include <arch/arm/CortexM/scb.h>
#include <arch/arm/CortexM/nvic.h>
#include <arch/arm/CortexM/memory_map.h>
#include <arch/arm/CortexM/gdb_stub.h>
#include <arch/arm/CortexM/asm_inline.h>
#endif
#ifdef __cplusplus
}
#endif
#endif /* _ARM_ARCH__H_ */

46
include/arch/cpu.h Normal file
View file

@ -0,0 +1,46 @@
/* cpu.h - automatically selects the correct arch.h file to include */
/*
* Copyright (c) 1997-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ARCHCPU_H__
#define __ARCHCPU_H__
#if defined(VXMICRO_ARCH_x86)
#include <arch/x86/arch.h>
#elif defined(VXMICRO_ARCH_arm)
#include <arch/arm/arch.h>
#elif defined(VXMICRO_ARCH_arc)
#include <arch/arc/arch.h>
#else
#error "Unknown VXMICRO_ARCH"
#endif
#endif /* __ARCHCPU_H__ */

102
include/arch/private.h Normal file
View file

@ -0,0 +1,102 @@
/* nanokernel/private.h */
/*
* Copyright (c) 1997-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __NANOPRIVATE_H__
#define __NANOPRIVATE_H__
#ifdef __cplusplus
extern "C" {
#endif
typedef struct s_CCS tCCS;
struct _nano_queue {
void *head;
void *tail;
};
struct nano_sem {
struct _nano_queue wait_q;
int nsig;
};
struct nano_lifo {
struct _nano_queue wait_q;
void *list;
};
struct nano_fifo {
union {
struct _nano_queue wait_q;
struct _nano_queue data_q;
};
int stat;
};
struct nano_stack {
tCCS *fiber;
uint32_t *base;
uint32_t *next;
};
struct nano_timer {
struct nano_timer *link;
uint32_t ticks;
struct nano_lifo lifo;
void *userData;
};
/* context entry point function typedef */
typedef void *_ContextArg;
typedef void (*_ContextEntry)(_ContextArg arg1,
_ContextArg arg2,
_ContextArg arg3);
/* Private API to set and clear essential fiber/task flag */
extern void _NanoEssentialContextSet(void);
extern void _NanoEssentialContextClear(void);
/* Private API to clean up when a context is aborted */
#if defined(CONFIG_CONTEXT_MONITOR)
extern void _context_exit(tCCS *ccs);
#else
#define _context_exit(ccs) \
do {/* nothing */ \
} while (0)
#endif /* CONFIG_CONTEXT_MONITOR */
#ifdef __cplusplus
}
#endif
#endif /* __NANOPRIVATE_H__ */

71
include/arch/x86/Intelprc.h Normal file
View file

@ -0,0 +1,71 @@
/* Intelprc.h - IA-32 specific definitions for cputype.h */
/*
* Copyright (c) 2010-2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This file is included by cputype.h when the VXMICRO_ARCH_x86 macro is defined,
i.e. whenever a build for the IA-32 architecture is being performed. This
file shall only contain the CPU/compiler specific definitions that are
necessary to build the EMBEDDED kernel library.
*/
#ifndef _INTELPRC_H
#define _INTELPRC_H
#ifdef __cplusplus
extern "C"
{
#endif
#define OCTET_TO_SIZEOFUNIT(X) (X) /* byte addressing */
#define SIZEOFUNIT_TO_OCTET(X) (X)
#include <stdint.h>
#include <toolchain.h>
#include <misc/util.h>
#include <arch/x86/addr_types.h>
#include <arch/x86/asm_inline.h>
#include <drivers/system_timer.h> /* timer_driver() needed by kernel_main.c */
/*
* Notification event reserved for use by GDB Agent.
* It is used to signal the agent notification task whenever
* a task has been stopped by the agent.
*/
#define GDB_NOTIFICATION_EVENT 1
#ifdef __cplusplus
}
#endif
#endif /* _INTELPRC_H */

39
include/arch/x86/addr_types.h Normal file
View file

@ -0,0 +1,39 @@
/* x86 address types (virtual, physical, etc) definitions */
/*
* Copyright (c) 2015 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _x86_addr_types__h_
#define _x86_addr_types__h_
typedef unsigned int PHYS_ADDR;
typedef unsigned int VIRT_ADDR;
#endif /* _x86_addr_types__h_ */

401
include/arch/x86/arch.h Normal file
View file

@ -0,0 +1,401 @@
/* arch.h - IA-32 specific nanokernel interface header */
/*
* Copyright (c) 2010-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This header contains the IA-32 specific nanokernel interface. It is included
by the generic nanokernel interface header (nanokernel.h)
*/
#ifndef _ARCH_IFACE_H
#define _ARCH_IFACE_H
/* WARNING: must include nanokernel.h before this file */
#ifndef _ASMLANGUAGE
#include <arch/x86/Intelprc.h>
#endif
/*
* Macro used internally by NANO_CPU_INT_REGISTER and NANO_CPU_INT_REGISTER_ASM.
* Not meant to be used explicitly by BSP, driver or application code.
*/
#define MK_ISR_NAME(x) __isr__##x
#ifndef _ASMLANGUAGE
/* interrupt/exception/error related definitions */
#define _INT_STUB_SIZE 0x2b
/*
* Performance optimization
*
* Macro PERF_OPT is defined if project is compiled with option other than
* size optimization ("-Os" for GCC, "-XO -Xsize-opt" for Diab). If the
* last of the compiler options is the size optimization, PERF_OPT is not
* defined and the project is optimized for size, hence the stub should be
* aligned to 1 and not 16.
*/
#ifdef PERF_OPT
#define _INT_STUB_ALIGN 16
#else
#define _INT_STUB_ALIGN 1
#endif
typedef unsigned char __attribute__((aligned(_INT_STUB_ALIGN)))
NANO_INT_STUB[_INT_STUB_SIZE];
typedef struct s_isrList {
void *fnc; /* Address of ISR/stub */
unsigned int vec; /* Vector number associated with ISR/stub */
unsigned int dpl; /* Privilege level associated with ISR/stub */
} ISR_LIST;
/*******************************************************************************
*
* NANO_CPU_INT_REGISTER - connect a routine to an interrupt vector
*
* This macro "connects" the specified routine, <r>, to the specified interrupt
* vector, <v> using the descriptor privilege level <d>. On the IA-32
* architecture, an interrupt vector is a value from 0 to 255. This macro
* populates the special intList section with the address of the routine, the
* vector number and the descriptor privilege level. The genIdt tool then picks
* up this information and generates an actual IDT entry with this information
* properly encoded. This macro replaces the _IntVecSet () routine in static
* interrupt systems.
*
* The <d> argument specifies the privilege level for the interrupt-gate
* descriptor; (hardware) interrupts and exceptions should specify a level of 0,
* whereas handlers for user-mode software generated interrupts should specify 3.
*
* RETURNS: N/A
*
*/
#define NANO_CPU_INT_REGISTER(r, v, d) \
ISR_LIST __attribute__((section(".intList"))) MK_ISR_NAME(r) = {&r, v, d}
/*
* Macro to declare a dynamic interrupt stub. Using the macro places the stub
* in the .intStubSection which is located in the image according to the kernel
* configuration.
*/
#define NANO_CPU_INT_STUB_DECL(s) \
_NODATA_SECTION(.intStubSect) NANO_INT_STUB(s)
/*
* A pointer to an "exception stack frame" (ESF) is passed as an argument
* to exception handlers registered via nanoCpuExcConnect(). When an exception
* occurs while PL=0, then only the EIP, CS, and EFLAGS are pushed onto the stack.
* The least significant pair of bits in the CS value should be examined to
* determine whether the exception occured while PL=3, in which case the ESP and
* SS values will also be present in the ESF. If the exception occurred while
* in PL=0, neither the SS nor ESP values will be present in the ESF.
*
* The exception stack frame includes the volatile registers EAX, ECX, and EDX
* pushed on the stack by _ExcEnt().
*
* It also contains the value of CR2, used when the exception is a page fault.
* Since that register is shared amongst threads of execution, it might get
* overwritten if another thread is context-switched in and then itself
* page-faults before the first thread has time to read CR2.
*
* If configured for host-based debug tools such as GDB, the 4 non-volatile
* registers (EDI, ESI, EBX, EBP) are also pushed by _ExcEnt()
* for use by the debug tools.
*/
typedef struct nanoEsf {
unsigned int cr2; /* putting cr2 here allows discarding it and pEsf in
* one instruction */
#ifdef CONFIG_GDB_INFO
unsigned int ebp;
unsigned int ebx;
unsigned int esi;
unsigned int edi;
#endif /* CONFIG_GDB_INFO */
unsigned int edx;
unsigned int ecx;
unsigned int eax;
unsigned int errorCode;
unsigned int eip;
unsigned int cs;
unsigned int eflags;
unsigned int esp;
unsigned int ss;
} NANO_ESF;
/*
* An "interrupt stack frame" (ISF) as constructed by the processor
* and the interrupt wrapper function _IntExit(). When an interrupt
* occurs while PL=0, only the EIP, CS, and EFLAGS are pushed onto the stack.
* The least significant pair of bits in the CS value should be examined to
* determine whether the exception occurred while PL=3, in which case the ESP
* and SS values will also be present in the ESF. If the exception occurred
* while in PL=0, neither the SS nor ESP values will be present in the ISF.
*
* The interrupt stack frame includes the volatile registers EAX, ECX, and EDX
* pushed on the stack by _IntExit()..
*
* The host-based debug tools such as GDB do not require the 4 non-volatile
* registers (EDI, ESI, EBX, EBP) to be preserved during an interrupt.
* The register values saved/restored by _Swap() called from _IntExit() are
* sufficient.
*/
typedef struct nanoIsf {
unsigned int edx;
unsigned int ecx;
unsigned int eax;
unsigned int eip;
unsigned int cs;
unsigned int eflags;
unsigned int esp;
unsigned int ss;
} NANO_ISF;
#endif /* !_ASMLANGUAGE */
/*
* Reason codes passed to both _NanoFatalErrorHandler()
* and _SysFatalErrorHandler().
*/
#define _NANO_ERR_SPURIOUS_INT (0) /* Unhandled exception/interrupt */
#define _NANO_ERR_PAGE_FAULT (1) /* Page fault */
#define _NANO_ERR_GEN_PROT_FAULT (2) /* General protection fault */
#define _NANO_ERR_INVALID_TASK_EXIT (3) /* Invalid task exit */
#define _NANO_ERR_STACK_CHK_FAIL (4) /* Stack corruption detected */
#define _NANO_ERR_INVALID_STRING_OP (5) /* Invalid string operation */
#ifndef _ASMLANGUAGE
#ifdef CONFIG_NO_ISRS
static inline unsigned int irq_lock(void) {return 1;}
static inline void irq_unlock(unsigned int key) {}
#define irq_lock_inline irq_lock
#define irq_unlock_inline irq_unlock
#else /* CONFIG_NO_ISRS */
#ifdef CONFIG_INT_LATENCY_BENCHMARK
void _int_latency_start(void);
void _int_latency_stop(void);
#endif
/*******************************************************************************
*
* irq_lock_inline - disable all interrupts on the CPU (inline)
*
* This routine disables interrupts. It can be called from either interrupt,
* task or fiber level. This routine returns an architecture-dependent
* lock-out key representing the "interrupt disable state" prior to the call;
* this key can be passed to irq_unlock_inline() to re-enable interrupts.
*
* The lock-out key should only be used as the argument to the
* irq_unlock_inline() API. It should never be used to manually re-enable
* interrupts or to inspect or manipulate the contents of the source register.
*
* WARNINGS
* Invoking a VxMicro routine with interrupts locked may result in
* interrupts being re-enabled for an unspecified period of time. If the
* called routine blocks, interrupts will be re-enabled while another
* context executes, or while the system is idle.
*
* The "interrupt disable state" is an attribute of a context. Thus, if a
* fiber or task disables interrupts and subsequently invokes a VxMicro
* system routine that causes the calling context to block, the interrupt
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
*/
static inline __attribute__((always_inline))
unsigned int irq_lock_inline(void)
{
unsigned int key = _do_irq_lock_inline();
#ifdef CONFIG_INT_LATENCY_BENCHMARK
_int_latency_start();
#endif
return key;
}
/*******************************************************************************
*
* irq_unlock_inline - enable all interrupts on the CPU (inline)
*
* This routine re-enables interrupts on the CPU. The <key> parameter
* is an architecture-dependent lock-out key that is returned by a previous
* invocation of irq_lock_inline().
*
* This routine can be called from either interrupt, task or fiber level.
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static inline __attribute__((always_inline))
void irq_unlock_inline(unsigned int key)
{
if (!(key & 0x200)) {
return;
}
#ifdef CONFIG_INT_LATENCY_BENCHMARK
_int_latency_stop();
#endif
_do_irq_unlock_inline();
return;
}
#endif /* CONFIG_NO_ISRS */
/* interrupt/exception/error related definitions */
typedef void (*NANO_EOI_GET_FUNC) (void *);
/*
* The NANO_SOFT_IRQ macro must be used as the value for the <irq> parameter
* to irq_connect() when connecting to a software generated interrupt.
*/
#define NANO_SOFT_IRQ ((unsigned int) (-1))
#ifdef CONFIG_FP_SHARING
/* Definitions for the 'options' parameter to the nanoFiberStart() API */
#define USE_FP 0x10 /* context uses floating point unit */
#ifdef CONFIG_SSE
#define USE_SSE 0x20 /* context uses SSEx instructions */
#endif /* CONFIG_SSE */
#endif /* CONFIG_FP_SHARING */
extern void _nano_fiber_swap(void);
extern unsigned int find_first_set(unsigned int op);
extern unsigned int find_last_set(unsigned int op);
extern void irq_handler_set(unsigned int vector,
void (*oldRoutine)(void *parameter),
void (*newRoutine)(void *parameter),
void *parameter);
extern int irq_connect(unsigned int irq,
unsigned int priority,
void (*routine)(void *parameter),
void *parameter,
NANO_INT_STUB pIntStubMem);
/*
* irq_enable() : enable a specific IRQ
* irq_disable() : disable a specific IRQ
* irq_lock() : lock out all interrupts
* irq_unlock() : unlock all interrupts
*/
extern void irq_enable(unsigned int irq);
extern void irq_disable(unsigned int irq);
#ifndef CONFIG_NO_ISRS
extern int irq_lock(void);
extern void irq_unlock(int key);
#endif /* CONFIG_NO_ISRS */
#ifdef CONFIG_FP_SHARING
/*
* Dynamically enable/disable the capability of a context to share floating
* point hardware resources. The same "floating point" options accepted by
* nanoFiberStart() are accepted by these APIs (i.e. USE_FP and USE_SSE).
*/
extern void fiber_float_enable(nano_context_id_t ctx, unsigned int options);
extern void task_float_enable(nano_context_id_t ctx, unsigned int options);
extern void fiber_float_disable(nano_context_id_t ctx);
extern void task_float_disable(nano_context_id_t ctx);
#endif /* CONFIG_FP_SHARING */
#include <stddef.h> /* for size_t */
#ifdef CONFIG_NANOKERNEL
extern void nano_cpu_idle(void);
#endif
/* Nanokernel provided routine to report any detected fatal error. */
extern FUNC_NORETURN void _NanoFatalErrorHandler(unsigned int reason,
const NANO_ESF *pEsf);
/* User provided routine to handle any detected fatal error post reporting. */
extern FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
const NANO_ESF *pEsf);
/* Dummy ESF for fatal errors that would otherwise not have an ESF */
extern const NANO_ESF _default_esf;
/*
* BSP provided routine which kernel invokes to configure an interrupt vector
* of the specified priority; the BSP allocates an interrupt vector, programs
* hardware to route interrupt requests on the specified irq to that vector,
* and returns the vector number along with its associated BOI/EOI information
*/
extern int _SysIntVecAlloc(unsigned int irq,
unsigned int priority,
NANO_EOI_GET_FUNC *boiRtn,
NANO_EOI_GET_FUNC *eoiRtn,
void **boiRtnParm,
void **eoiRtnParm,
unsigned char *boiParamRequired,
unsigned char *eoiParamRequired
);
/* functions provided by the kernel for usage by the BSP's _SysIntVecAlloc() */
extern int _IntVecAlloc(unsigned int priority);
extern void _IntVecMarkAllocated(unsigned int vector);
extern void _IntVecMarkFree(unsigned int vector);
#endif /* !_ASMLANGUAGE */
/* Segment selector defintions are shared */
#include "segselect.h"
#endif /* _ARCH_IFACE_H */

52
include/arch/x86/asm.h Normal file
View file

@ -0,0 +1,52 @@
/* asm.h - x86 tool dependent headers */
/*
* Copyright (c) 2007-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __INCsysX86Asmh
#define __INCsysX86Asmh
#include <toolchain.h>
#include <sections.h>
/* offsets from stack pointer to function arguments */
#define SP_ARG0 0
#define SP_ARG1 4
#define SP_ARG2 8
#define SP_ARG3 12
#define SP_ARG4 16
#define SP_ARG5 20
#define SP_ARG6 24
#define SP_ARG7 28
#define SP_ARG8 32
#endif /* __INCsysX86Asmh */

47
include/arch/x86/asm_inline.h Normal file
View file

@ -0,0 +1,47 @@
/* Intel x86 inline assembler functions and macros for public functions */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _ASM_INLINE_PUBLIC_H
#define _ASM_INLINE_PUBLIC_H
/*
* The file must not be included directly
* Include nanokernel/cpu.h instead
*/
#if defined(__GNUC__)
#include <arch/x86/asm_inline_gcc.h>
#else
#include <arch/x86/asm_inline_other.h>
#endif
#endif /* _ASM_INLINE_PUBLIC_H */

462
include/arch/x86/asm_inline_gcc.h Normal file
View file

@ -0,0 +1,462 @@
/* Intel x86 GCC specific public inline assembler functions and macros */
/*
* Copyright (c) 2015, Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/* Either public functions or macros or invoked by public functions */
#ifndef _ASM_INLINE_GCC_PUBLIC_GCC_H
#define _ASM_INLINE_GCC_PUBLIC_GCC_H
/*
* The file must not be included directly
* Include nanokernel/cpu.h instead
*/
#ifndef _ASMLANGUAGE
#include <stdint.h>
#include <stddef.h>
/*******************************************************************************
*
* _do_irq_lock_inline - disable all interrupts on the CPU (inline)
*
* This routine disables interrupts. It can be called from either interrupt,
* task or fiber level. This routine returns an architecture-dependent
* lock-out key representing the "interrupt disable state" prior to the call;
* this key can be passed to irq_unlock_inline() to re-enable interrupts.
*
* The lock-out key should only be used as the argument to the
* irq_unlock_inline() API. It should never be used to manually re-enable
* interrupts or to inspect or manipulate the contents of the source register.
*
* WARNINGS
* Invoking a VxMicro routine with interrupts locked may result in
* interrupts being re-enabled for an unspecified period of time. If the
* called routine blocks, interrupts will be re-enabled while another
* context executes, or while the system is idle.
*
* The "interrupt disable state" is an attribute of a context. Thus, if a
* fiber or task disables interrupts and subsequently invokes a VxMicro
* system routine that causes the calling context to block, the interrupt
* disable state will be restored when the context is later rescheduled
* for execution.
*
* RETURNS: An architecture-dependent lock-out key representing the
* "interrupt disable state" prior to the call.
*
* \NOMANUAL
*/
static inline __attribute__((always_inline))
unsigned int _do_irq_lock_inline(void)
{
unsigned int key;
__asm__ volatile (
"pushfl;\n\t"
"cli;\n\t"
"popl %0;\n\t"
: "=g" (key)
:
: "memory"
);
return key;
}
/*******************************************************************************
*
* _do_irq_unlock_inline - enable all interrupts on the CPU (inline)
*
* This routine can be called from either interrupt, task or fiber level.
* Invoked by kernel or by irq_unlock_inline()
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static inline __attribute__((always_inline))
void _do_irq_unlock_inline(void)
{
__asm__ volatile (
"sti;\n\t"
: :
);
}
/*******************************************************************************
*
* find_first_set_inline - find first set bit searching from the LSB (inline)
*
* This routine finds the first bit set in the argument passed it and
* returns the index of that bit. Bits are numbered starting
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed
* and leverage the fact that the 'bsfl' doesn't modify the destination operand
* when the source operand is zero. The "bitpos" variable can be preloaded
* into the destination register, and given the unconditional ++bitpos that
* is performed after the 'cmovzl', the correct results are yielded.
*/
static inline __attribute__((always_inline))
unsigned int find_first_set_inline (unsigned int op)
{
int bitpos;
__asm__ volatile (
#if !defined(CONFIG_CMOV_UNSUPPORTED)
"bsfl %1, %0;\n\t"
"cmovzl %2, %0;\n\t"
: "=r" (bitpos)
: "rm" (op), "r" (-1)
: "cc"
#else
"bsfl %1, %0;\n\t"
"jnz 1f;\n\t"
"movl $-1, %0;\n\t"
"1:\n\t"
: "=r" (bitpos)
: "rm" (op)
: "cc"
#endif /* !CONFIG_CMOV_UNSUPPORTED */
);
return (bitpos + 1);
}
/*******************************************************************************
*
* find_last_set_inline - find first set bit searching from the MSB (inline)
*
* This routine finds the first bit set in the argument passed it and
* returns the index of that bit. Bits are numbered starting
* at 1 from the least significant bit to 32 for the most significant bit.
* A return value of zero indicates that the value passed is zero.
*
* RETURNS: bit position from 1 to 32, or 0 if the argument is zero.
*
* INTERNAL
* For Intel64 (x86_64) architectures, the 'cmovzl' can be removed
* and leverage the fact that the 'bsfl' doesn't modify the destination operand
* when the source operand is zero. The "bitpos" variable can be preloaded
* into the destination register, and given the unconditional ++bitpos that
* is performed after the 'cmovzl', the correct results are yielded.
*/
static inline inline __attribute__((always_inline))
unsigned int find_last_set_inline (unsigned int op)
{
int bitpos;
__asm__ volatile (
#if !defined(CONFIG_CMOV_UNSUPPORTED)
"bsrl %1, %0;\n\t"
"cmovzl %2, %0;\n\t"
: "=r" (bitpos)
: "rm" (op), "r" (-1)
#else
"bsrl %1, %0;\n\t"
"jnz 1f;\n\t"
"movl $-1, %0;\n\t"
"1:\n\t"
: "=r" (bitpos)
: "rm" (op)
: "cc"
#endif /* CONFIG_CMOV_UNSUPPORTED */
);
return (bitpos + 1);
}
/********************************************************
*
* _NanoTscRead - read timestamp register ensuring serialization
*/
static inline uint64_t _NanoTscRead(void)
{
union {
struct {
uint32_t lo;
uint32_t hi;
};
uint64_t value;
} rv;
/* rdtsc & cpuid clobbers eax, ebx, ecx and edx registers */
__asm__ volatile (/* serialize */
"xorl %%eax,%%eax;\n\t"
"cpuid;\n\t"
:
:
: "%eax", "%ebx", "%ecx", "%edx"
);
/*
* We cannot use "=A", since this would use %rax on x86_64 and
* return only the lower 32bits of the TSC
*/
__asm__ volatile ("rdtsc" : "=a" (rv.lo), "=d" (rv.hi));
return rv.value;
}
/*******************************************************************************
*
* _do_read_cpu_timestamp - get a 32 bit CPU timestamp counter
*
* RETURNS: a 32-bit number
*/
static inline inline __attribute__((always_inline))
uint32_t _do_read_cpu_timestamp32(void)
{
uint32_t rv;
__asm__ volatile("rdtsc" : "=a"(rv) : : "%edx");
return rv;
}
/*******************************************************************************
*
* sys_out8 - output a byte to an IA-32 I/O port
*
* This function issues the 'out' instruction to write a byte to the specified
* I/O port.
*
* RETURNS: N/A
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
void sys_out8(unsigned char data, unsigned int port)
{
__asm__ volatile("outb %%al, %%dx;\n\t" : : "a"(data), "d"(port));
}
/*******************************************************************************
*
* sys_in8 - input a byte from an IA-32 I/O port
*
* This function issues the 'in' instruction to read a byte from the specified
* I/O port.
*
* RETURNS: the byte read from the specified I/O port
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
unsigned char sys_in8(unsigned int port)
{
char retByte;
__asm__ volatile("inb %%dx, %%al;\n\t" : "=a"(retByte) : "d"(port));
return retByte;
}
/*******************************************************************************
*
* sys_out16 - output a word to an IA-32 I/O port
*
* This function issues the 'out' instruction to write a word to the
* specified I/O port.
*
* RETURNS: N/A
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
void sys_out16(unsigned short data, unsigned int port)
{
__asm__ volatile("outw %%ax, %%dx;\n\t" : : "a"(data), "d"(port));
}
/*******************************************************************************
*
* sys_in16 - input a word from an IA-32 I/O port
*
* This function issues the 'in' instruction to read a word from the
* specified I/O port.
*
* RETURNS: the word read from the specified I/O port
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
unsigned short sys_in16(unsigned int port)
{
unsigned short retWord;
__asm__ volatile("inw %%dx, %%ax;\n\t" : "=a"(retWord) : "d"(port));
return retWord;
}
/*******************************************************************************
*
* sys_out32 - output a long word to an IA-32 I/O port
*
* This function issues the 'out' instruction to write a long word to the
* specified I/O port.
*
* RETURNS: N/A
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
void sys_out32(unsigned int data, unsigned int port)
{
__asm__ volatile("outl %%eax, %%dx;\n\t" : : "a"(data), "d"(port));
}
/*******************************************************************************
*
* sys_in32 - input a long word from an IA-32 I/O port
*
* This function issues the 'in' instruction to read a long word from the
* specified I/O port.
*
* RETURNS: the long read from the specified I/O port
*
* NOMANUAL
*/
static inline inline __attribute__((always_inline))
unsigned long sys_in32(unsigned int port)
{
unsigned long retLong;
__asm__ volatile("inl %%dx, %%eax;\n\t" : "=a"(retLong) : "d"(port));
return retLong;
}
/********************************************************
*
* k_memcpy - copy memory area
*
* Copy _n bytes from source _s to destination _d
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static inline void k_memcpy(void *_d, const void *_s, size_t _n)
{
/* _d & _s must be aligned to use movsl. */
#ifndef CONFIG_UNALIGNED_WRITE_UNSUPPORTED
if ((_n&3) == 0) {
/* _n is multiple of words, much more efficient to do word moves */
_n >>= 2;
__asm__ volatile ("rep movsl" :
"+D" (_d), "+S" (_s), "+c" (_n) :
:
"cc", "memory");
} else
#endif /* CONFIG_UNALIGNED_WRITE_UNSUPPORTED */
{
__asm__ volatile ("rep movsb" :
"+D" (_d), "+S" (_s), "+c" (_n) :
:
"cc", "memory");
}
}
/********************************************************
*
* k_memset - set memory area
*
* Set _n bytes in the area _d to value _v
*
* RETURNS: N/A
*
* \NOMANUAL
*/
static inline void k_memset(void *_d, int _v, size_t _n)
{
/* _d must be aligned to use stosl. */
#ifndef CONFIG_UNALIGNED_WRITE_UNSUPPORTED
if ((_n&3) == 0) {
/* _n is multiple of words, much more efficient to do word stores */
_n >>= 2;
_v |= _v<<8;
_v |= _v<<16;
__asm__ volatile ("rep stosl" :
"+D" (_d), "+c" (_n) :
"a" (_v) :
"cc", "memory");
} else
#endif /* CONFIG_UNALIGNED_WRITE_UNSUPPORTED */
{
__asm__ volatile ("rep stosb" :
"+D" (_d), "+c" (_n) :
"a" (_v) :
"cc", "memory");
}
}
#endif /* _ASMLANGUAGE */
#endif /* _ASM_INLINE_GCC_PUBLIC_GCC_H */

219
include/arch/x86/linker-common-sections.h Normal file
View file

@ -0,0 +1,219 @@
/* linker-common-sections.h - common linker sections in VxMicro */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
This script defines where the various sections of a VxMicro image go in memory.
It is usable by most BSPs supported in VxMicro. This file is used by the linker.
This script places the various sections of the image according to what feature
is used in VxMicro.
For a build that does not use the execute in place (XIP) feature, the script
generates an image suitable for loading into and executing from RAM by placing
all the sections adjacent to each other. There is also no separate load
address for the DATA section which means it doesn't have to be copied into RAM.
For builds using XIP, there is a different load memory address (LMA) and
virtual memory address (VMA) for the DATA section. In this case the DATA
section is copied into RAM at runtime.
When building an XIP image the data section is placed into ROM. In this case,
the LMA is set to __data_rom_start so the data section is concatenated at the
end of the RODATA section. At runtime, the DATA section is copied into the RAM
region so it can be accessed with read and write permission.
Most symbols defined in the sections below are subject to be referenced in the
VxMicro image. If a symbol is used but not defined the linker will emit an
undefined symbol error.
Please do not change the order of the section as the nanokernel expects this
order when programming the MMU.
*/
#define _LINKER
#define _ASMLANGUAGE /* Needed to include mmustructs.h */
#include <linker-defs.h>
#include <offsets.h>
#include <misc/util.h>
#define MMU_PAGE_SIZE KB(4)
#include <linker-tool.h>
/* SECTIONS definitions */
SECTIONS
{
GROUP_START(ROMABLE_REGION)
SECTION_PROLOGUE(_TEXT_SECTION_NAME, (OPTIONAL),)
{
*(.text_start)
*(".text_start.*")
*(.text)
*(".text.*")
*(.eh_frame)
*(.init)
*(.fini)
*(.eini)
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_CTOR_SECTION_NAME, (OPTIONAL),)
{
/*
* The compiler fills the constructor pointers table below, hence symbol
* __CTOR_LIST__ must be aligned on 4 byte boundary.
* To align with the C++ standard, the first element of the array
* contains the number of actual constructors. The last element is
* NULL.
*/
. = ALIGN(4);
__CTOR_LIST__ = .;
LONG((__CTOR_END__ - __CTOR_LIST__) / 4 - 2)
KEEP(*(SORT_BY_NAME(".ctors*")))
LONG(0)
__CTOR_END__ = .;
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)
} GROUP_LINK_IN(ROMABLE_REGION)
SECTION_PROLOGUE(_RODATA_SECTION_NAME, (OPTIONAL),)
{
*(.rodata)
*(".rodata.*")
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)
} GROUP_LINK_IN(ROMABLE_REGION)
__data_rom_start = ALIGN(4); /* XIP imaged DATA ROM start addr */
GROUP_END(ROMABLE_REGION)
/* RAM */
GROUP_START(RAM)
#if defined(CONFIG_XIP)
SECTION_AT_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),,__data_rom_start)
#else
SECTION_PROLOGUE(_DATA_SECTION_NAME, (OPTIONAL),)
#endif
{
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)
__data_ram_start = .;
*(.data)
*(".data.*")
IDT_MEMORY
. = ALIGN(4);
} GROUP_LINK_IN(RAM)
__data_ram_end = .;
SECTION_PROLOGUE(_BSS_SECTION_NAME, (NOLOAD OPTIONAL),)
{
/*
* For performance, BSS section is forced to be both 4 byte aligned and
* a multiple of 4 bytes.
*/
. = ALIGN(4);
__bss_start = .;
*(.bss)
*(".bss.*")
COMMON_SYMBOLS
/*
* Ensure the true BSS section ends on a 4 byte boundary. When the BSP
* clears this memory it is done in words only and doesn't clear any
* potential left over bytes. Rather than adding code to do this it is
* simpler to pad out the end of the section. We only waste a maximum
* of 3 bytes.
*/
. = ALIGN(4);
__bss_end = .;
KEXEC_PGALIGN_PAD(MMU_PAGE_SIZE)
} GROUP_LINK_IN(RAM)
#ifdef CONFIG_XIP
/*
* Ensure linker keeps sections in correct order, despite the fact
* the previous section specified a load address and this no-load
* section doesn't.
*/
GROUP_FOLLOWS_AT(RAM)
#endif
SECTION_PROLOGUE(_NOINIT_SECTION_NAME, (NOLOAD OPTIONAL),)
{
/*
* This section is used for non-intialized objects that
* will not be cleared during the boot process.
*/
*(.noinit)
*(".noinit.*")
INT_STUB_NOINIT
} GROUP_LINK_IN(RAM)
/* Define linker symbols */
_end = .; /* end of image */
. = ALIGN(MMU_PAGE_SIZE);
__bss_num_words = (__bss_end - __bss_start) >> 2;
GROUP_END(RAM)
/* static interrupts */
SECTION_PROLOGUE(intList, (OPTIONAL),)
{
KEEP(*(.spurIsr))
KEEP(*(.spurNoErrIsr))
__INT_LIST_START__ = .;
LONG((__INT_LIST_END__ - __INT_LIST_START__) / __ISR_LIST_SIZEOF)
KEEP(*(.intList))
__INT_LIST_END__ = .;
} > IDT_LIST
}
#ifdef CONFIG_XIP
/*
* Round up number of words for DATA section to ensure that XIP copies the
* entire data section. XIP copy is done in words only, so there may be up
* to 3 extra bytes copied in next section (BSS). At run time, the XIP copy
* is done first followed by clearing the BSS section.
*/
__data_size = (__data_ram_end - __data_ram_start);
__data_num_words = (__data_size + 3) >> 2;
#endif

65
include/arch/x86/linker-defs-arch.h Normal file
View file

@ -0,0 +1,65 @@
/* linker-defs-arch.h - Intel commonly used macro and defines for linker script */
/*
* Copyright (c) 2013-2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
/*
DESCRIPTION
Commonly used macros and defines for linker script.
*/
#ifndef _LINKERDEFSARCH_H
#define _LINKERDEFSARCH_H
#include <toolchain.h>
#define INT_STUB_NOINIT KEEP(*(.intStubSect))
#ifdef FINAL_LINK
/* Use the real IDT */
#define STATIC_IDT KEEP(*(staticIdt))
#else
/*
* Save space for the real IDT to prevent symbols from shifting. Note that
* an IDT entry is 8 bytes in size.
*/
#define STATIC_IDT . += (8 * CONFIG_IDT_NUM_VECTORS);
#endif
/*
* The x86 manual recommends aligning the IDT on 8 byte boundary. This also
* ensures that individual entries do not span a page boundary which the
* interrupt management code relies on.
*/
#define IDT_MEMORY \
. = ALIGN(8);\
_idt_base_address = .;\
STATIC_IDT
#endif /* _LINKERDEFSARCH_H */

95
include/arch/x86/linker-epilog.h Normal file
View file

@ -0,0 +1,95 @@
/* linker-epilog.h - defines structures that conclude linker script */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1) Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2) Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3) Neither the name of Wind River Systems nor the names of its contributors
* may be used to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef _LINKER_EPILOG_H
#define _LINKER_EPILOG_H
#include <linker-defs.h>
#ifdef _LINKER
/*
* DIAB linker does not support multiple SECTIONS commands
* in linker script
*/
#if defined(__GCC_LINKER_CMD__)
/*
* The following guard prevents usage of orphaned sections --
* the sections that are not explicitly mentioned in the linker script
*/
SECTIONS
{
/* list all debugging sections that needed in resulting ELF */
.shstrtab 0 (OPTIONAL): { *(.shstrtab) }
.symtab 0 (OPTIONAL): { *(.symtab) }
.strtab 0 (OPTIONAL): { *(.strtab) }
.iplt 0 (OPTIONAL): { *(.iplt) }
.igot.plt 0 (OPTIONAL): { *(.igot.plt) }
.rel.plt 0 (OPTIONAL): { *(.rel.plt) }
.rela.plt 0 (OPTIONAL): { *(.rela.plt) }
.rel.dyn 0 (OPTIONAL): { *(".rel.*") }
.rela.dyn 0 (OPTIONAL): { *(".rela.*") }
.comment 0 (OPTIONAL): { *(.comment) }
/* DWARF debugging sections */
/* DWARF 1 */
.debug 0 (OPTIONAL): { *(.debug) }
.line 0 (OPTIONAL): { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 (OPTIONAL): { *(.debug_aranges) }
.debug_pubnames 0 (OPTIONAL): { *(.debug_pubnames) }
.debug_pubtypes 0 (OPTIONAL): { *(.debug_pubtypes) }
/* DWARF 2 */
.debug_line 0 (OPTIONAL): { *(.debug_line) }
.debug_info 0 (OPTIONAL): { *(.debug_info) }
.debug_macinfo 0 (OPTIONAL): { *(.debug_macinfo) }
.debug_abbrev 0 (OPTIONAL): { *(.debug_abbrev) }
.debug_loc 0 (OPTIONAL): { *(.debug_loc) }
.debug_ranges 0 (OPTIONAL): { *(.debug_ranges) }
.debug_str 0 (OPTIONAL): { *(.debug_str) }
.debug_frame 0 (OPTIONAL): { *(.debug_frame) }
/* generate a linker error if orphan section is used */
.trashcan :
{
*(.*)
}
}
ASSERT(SIZEOF(.trashcan) == 0, "Section(s) undefined in the linker script used.")
#endif /* (__GCC_LINKER_CMD__) */
#endif /* _LINKER */
#endif /* _LINKER_EPILOG_H */

1
include/arch/x86/segselect.h Normal file
View file

@ -0,0 +1 @@
#include "../../../shared/include/nanokernel/x86/segselect.h"