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arm: add CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS kconfig flag

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Cortex-M0/M0+ do not have other faults than the hard fault at priority
-1, so they do not need to reserve a priority to allow exceptions to
trigger during handling of ISRs.

Change-Id: I479e439f7bcac70b4b2b787bcd744a4c65437e80
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
This commit is contained in:
Benjamin Walsh 2016-12-13 12:00:09 -05:00 • committed by Maureen Helm
commit c016252108
1 changed files with 10 additions and 0 deletions
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10
arch/arm/core/cortex_m/Kconfig
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@ -52,6 +52,14 @@ config CPU_CORTEX_M_HAS_BASEPRI
help
This option signifies the CPU has the BASEPRI register.
config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
bool
# Omit prompt to signify "hidden" option
default n
help
This option signifies the CPU faults other than the hard fault, and
needs to reserve a priority for them.
config CPU_CORTEX_M0_M0PLUS
bool
# Omit prompt to signify "hidden" option
@ -68,6 +76,7 @@ config CPU_CORTEX_M3_M4
select ATOMIC_OPERATIONS_BUILTIN
select ISA_THUMB2
select CPU_CORTEX_M_HAS_BASEPRI
select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
help
This option signifies the use of either a Cortex-M3 or Cortex-M4 CPU.
@ -106,6 +115,7 @@ config CPU_CORTEX_M7
select ATOMIC_OPERATIONS_BUILTIN
select ISA_THUMB2
select CPU_CORTEX_M_HAS_BASEPRI
select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS
help
This option signifies the use of a Cortex-M7 CPU