diff --git a/boards/arm/mps2/mps2_an521-common.dtsi b/boards/arm/mps2/mps2_an521-common.dtsi index 5b1959ff5fe..acd2be8da72 100644 --- a/boards/arm/mps2/mps2_an521-common.dtsi +++ b/boards/arm/mps2/mps2_an521-common.dtsi @@ -156,7 +156,7 @@ i2c_shield1: i2c@20d000 { }; gpio_led0: mps2_fpgaio@302000 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302000 0x4>; gpio-controller; @@ -165,16 +165,17 @@ gpio_led0: mps2_fpgaio@302000 { }; gpio_button: mps2_fpgaio@302008 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps2_fpgaio@30204c { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x30204c 0x4>; gpio-controller; diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml index 2e73e6b113a..e511285c190 100644 --- a/boards/arm/mps2/mps2_an521_cpu0.yaml +++ b/boards/arm/mps2/mps2_an521_cpu0.yaml @@ -15,7 +15,6 @@ supported: testing: default: true ignore_tags: - - drivers - bluetooth - net - timer diff --git a/boards/arm/mps2/mps2_base.dtsi b/boards/arm/mps2/mps2_base.dtsi index 4d8106aa912..0733b6e342d 100644 --- a/boards/arm/mps2/mps2_base.dtsi +++ b/boards/arm/mps2/mps2_base.dtsi @@ -236,7 +236,7 @@ }; gpio_led0: mps2_fpgaio@40028000 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x40028000 0x4>; gpio-controller; #gpio-cells = <1>; @@ -244,15 +244,16 @@ }; gpio_button: mps2_fpgaio@40028008 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x40028008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps2_fpgaio@4002804c { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x4002804c 0x4>; gpio-controller; #gpio-cells = <1>; diff --git a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi index 6fd5c7acd40..4fc90627eec 100644 --- a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi +++ b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi @@ -122,7 +122,7 @@ i2c_ddr4_eeprom: i2c@9208000 { }; gpio_led0: mps3_fpgaio@9302000 { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x9302000 0x4>; gpio-controller; @@ -131,16 +131,17 @@ gpio_led0: mps3_fpgaio@9302000 { }; gpio_button: mps3_fpgaio@9302008 { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x9302008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps3_fpgaio@930204c { - compatible = "arm,mps3-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x930204c 0x4>; gpio-controller; diff --git a/boards/arm/mps3/mps3_corstone300_fvp.yaml b/boards/arm/mps3/mps3_corstone300_fvp.yaml index 07c8c8a131e..0629af2dea9 100644 --- a/boards/arm/mps3/mps3_corstone300_fvp.yaml +++ b/boards/arm/mps3/mps3_corstone300_fvp.yaml @@ -17,7 +17,6 @@ supported: - gpio testing: ignore_tags: - - drivers - bluetooth - net - timer diff --git a/drivers/gpio/gpio_mmio32.c b/drivers/gpio/gpio_mmio32.c index 5244f45f29e..7c0c8e0c9ab 100644 --- a/drivers/gpio/gpio_mmio32.c +++ b/drivers/gpio/gpio_mmio32.c @@ -26,12 +26,30 @@ * gpio_port_write. */ -#include +#define DT_DRV_COMPAT arm_mmio32_gpio + #include #include -static int gpio_mmio32_config(const struct device *dev, - gpio_pin_t pin, gpio_flags_t flags) +#include + +struct gpio_mmio32_config { + /* gpio_driver_config needs to be first */ + struct gpio_driver_config common; + volatile uint32_t *reg; + uint32_t mask; + bool is_input; +}; + +struct gpio_mmio32_context { + /* gpio_driver_data needs to be first */ + struct gpio_driver_data common; + const struct gpio_mmio32_config *config; +}; + +int gpio_mmio32_init(const struct device *dev); + +static int gpio_mmio32_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { struct gpio_mmio32_context *context = dev->data; const struct gpio_mmio32_config *config = context->config; @@ -40,13 +58,19 @@ static int gpio_mmio32_config(const struct device *dev, return -EINVAL; /* Pin not in our validity mask */ } - if (flags & ~(GPIO_INPUT | GPIO_OUTPUT | - GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | + if (flags & ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH | GPIO_ACTIVE_LOW)) { /* We ignore direction and fake polarity, rest is unsupported */ return -ENOTSUP; } + if (config->is_input && ((flags & GPIO_OUTPUT) != 0)) { + return -ENOTSUP; + } + if (!config->is_input && ((flags & GPIO_INPUT) != 0)) { + return -ENOTSUP; + } + if ((flags & GPIO_OUTPUT) != 0) { unsigned int key; volatile uint32_t *reg = config->reg; @@ -73,9 +97,7 @@ static int gpio_mmio32_port_get_raw(const struct device *dev, uint32_t *value) return 0; } -static int gpio_mmio32_port_set_masked_raw(const struct device *dev, - uint32_t mask, - uint32_t value) +static int gpio_mmio32_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) { struct gpio_mmio32_context *context = dev->data; const struct gpio_mmio32_config *config = context->config; @@ -93,8 +115,7 @@ static int gpio_mmio32_port_set_masked_raw(const struct device *dev, return 0; } -static int gpio_mmio32_port_set_bits_raw(const struct device *dev, - uint32_t mask) +static int gpio_mmio32_port_set_bits_raw(const struct device *dev, uint32_t mask) { struct gpio_mmio32_context *context = dev->data; const struct gpio_mmio32_config *config = context->config; @@ -111,8 +132,7 @@ static int gpio_mmio32_port_set_bits_raw(const struct device *dev, return 0; } -static int gpio_mmio32_port_clear_bits_raw(const struct device *dev, - uint32_t mask) +static int gpio_mmio32_port_clear_bits_raw(const struct device *dev, uint32_t mask) { struct gpio_mmio32_context *context = dev->data; const struct gpio_mmio32_config *config = context->config; @@ -129,8 +149,7 @@ static int gpio_mmio32_port_clear_bits_raw(const struct device *dev, return 0; } -static int gpio_mmio32_port_toggle_bits(const struct device *dev, - uint32_t mask) +static int gpio_mmio32_port_toggle_bits(const struct device *dev, uint32_t mask) { struct gpio_mmio32_context *context = dev->data; const struct gpio_mmio32_config *config = context->config; @@ -147,8 +166,7 @@ static int gpio_mmio32_port_toggle_bits(const struct device *dev, return 0; } -int gpio_mmio_pin_interrupt_configure(const struct device *port, - gpio_pin_t pin, +int gpio_mmio32_pin_interrupt_configure(const struct device *port, gpio_pin_t pin, enum gpio_int_mode, enum gpio_int_trig) { return -ENOTSUP; @@ -161,7 +179,7 @@ DEVICE_API(gpio, gpio_mmio32_api) = { .port_set_bits_raw = gpio_mmio32_port_set_bits_raw, .port_clear_bits_raw = gpio_mmio32_port_clear_bits_raw, .port_toggle_bits = gpio_mmio32_port_toggle_bits, - .pin_interrupt_configure = gpio_mmio_pin_interrupt_configure, + .pin_interrupt_configure = gpio_mmio32_pin_interrupt_configure, }; int gpio_mmio32_init(const struct device *dev) @@ -173,3 +191,22 @@ int gpio_mmio32_init(const struct device *dev) return 0; } + +#define MMIO32_GPIO_DEVICE(n) \ + static struct gpio_mmio32_context gpio_mmio32_##n##_ctx; \ + \ + static const struct gpio_mmio32_config gpio_mmio32_##n##_cfg = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ + }, \ + .reg = (volatile uint32_t *)DT_INST_REG_ADDR(n), \ + .mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ + .is_input = DT_INST_PROP(n, direction_input), \ + }; \ + \ + DEVICE_DT_INST_DEFINE(n, gpio_mmio32_init, NULL, &gpio_mmio32_##n##_ctx, \ + &gpio_mmio32_##n##_cfg, PRE_KERNEL_1, \ + CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_mmio32_api); + +DT_INST_FOREACH_STATUS_OKAY(MMIO32_GPIO_DEVICE) diff --git a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mmio32-gpio.yaml similarity index 52% rename from dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml rename to dts/bindings/gpio/arm,mmio32-gpio.yaml index 1c91ef9ca2a..0a8692adef4 100644 --- a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml +++ b/dts/bindings/gpio/arm,mmio32-gpio.yaml @@ -1,6 +1,6 @@ -description: GPIO controller on ARM MPS2 FPGA +description: ARM MMIO32 GPIO -compatible: "arm,mps2-fpgaio-gpio" +compatible: "arm,mmio32-gpio" include: [gpio-controller.yaml, base.yaml] @@ -14,5 +14,9 @@ properties: "#gpio-cells": const: 1 + direction-input: + type: boolean + description: Marks this pin set as all input pins. + gpio-cells: - pin diff --git a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml deleted file mode 100644 index 8d93742f9ed..00000000000 --- a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml +++ /dev/null @@ -1,18 +0,0 @@ -description: GPIO controller on ARM MPS3 FPGA - -compatible: "arm,mps3-fpgaio-gpio" - -include: [gpio-controller.yaml, base.yaml] - -properties: - reg: - required: true - - ngpios: - required: true - - "#gpio-cells": - const: 1 - -gpio-cells: - - pin diff --git a/include/zephyr/drivers/gpio/gpio_mmio32.h b/include/zephyr/drivers/gpio/gpio_mmio32.h deleted file mode 100644 index 005f7205293..00000000000 --- a/include/zephyr/drivers/gpio/gpio_mmio32.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2016 Linaro Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ -#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ - -#include -#include -#include - -#ifdef __cplusplus -extern "C" { -#endif - -extern const struct gpio_driver_api gpio_mmio32_api; - -struct gpio_mmio32_config { - /* gpio_driver_config needs to be first */ - struct gpio_driver_config common; - volatile uint32_t *reg; - uint32_t mask; -}; - -struct gpio_mmio32_context { - /* gpio_driver_data needs to be first */ - struct gpio_driver_data common; - const struct gpio_mmio32_config *config; -}; - -int gpio_mmio32_init(const struct device *dev); - -#ifdef CONFIG_GPIO_MMIO32 - -/** - * Create a device object for accessing a simple 32-bit i/o register using the - * same APIs as GPIO drivers. - * - * @param node_id The devicetree node identifier. - * @param _address The address of the 32-bit i/o register the device will - * provide access to. - * @param _mask Mask of bits in the register that it is valid to access. - * E.g. 0xffffffffu to allow access to all of them. - * - */ -#define GPIO_MMIO32_INIT(node_id, _address, _mask) \ -static struct gpio_mmio32_context _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx); \ - \ -static const struct gpio_mmio32_config _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg) = { \ - .common = { \ - .port_pin_mask = _mask, \ - }, \ - .reg = (volatile uint32_t *)_address, \ - .mask = _mask, \ -}; \ - \ -DEVICE_DT_DEFINE(node_id, \ - &gpio_mmio32_init, \ - NULL, \ - &_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx), \ - &_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg), \ - PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \ - &gpio_mmio32_api) - - -#else /* CONFIG_GPIO_MMIO32 */ - -/* Null definition for when support not configured into kernel */ -#define GPIO_MMIO32_INIT(node_id, _address, _mask) - -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ */ diff --git a/soc/arm/mps2/soc.c b/soc/arm/mps2/soc.c index 343330d4515..a45e1815f3d 100644 --- a/soc/arm/mps2/soc.c +++ b/soc/arm/mps2/soc.c @@ -7,40 +7,24 @@ * SPDX-License-Identifier: Apache-2.0 */ -#include #include #include - -/* Setup GPIO drivers for accessing FPGAIO registers */ -#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio) -#define FPGAIO_INIT(n) \ - GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ - DT_REG_ADDR(FPGAIO_NODE(n)), \ - BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) - -/* We expect there to be 3 arm,mps2-fpgaio-gpio devices: - * led0, button, and misc - */ -FPGAIO_INIT(0); -FPGAIO_INIT(1); -FPGAIO_INIT(2); - /* (Secure System Control) Base Address */ -#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) -#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) -#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) -#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) +#define SSE_200_SYSTEM_CTRL_S_BASE (0x50021000UL) +#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114) +#define SSE_200_SYSTEM_CTRL_CPU_WAIT (SSE_200_SYSTEM_CTRL_S_BASE + 0x118) +#define SSE_200_CPU_ID_UNIT_BASE (0x5001F000UL) /* The base address that the application image will start at on the secondary * (non-TrustZone) Cortex-M33 mcu. */ -#define CPU1_FLASH_ADDRESS (0x38B000) +#define CPU1_FLASH_ADDRESS (0x38B000) /* The memory map offset for the application image, which is used * to determine the location of the reset vector at startup. */ -#define CPU1_FLASH_OFFSET (0x10000000) +#define CPU1_FLASH_OFFSET (0x10000000) /** * @brief Wake up CPU 1 from another CPU, this is platform specific. @@ -49,9 +33,7 @@ void wakeup_cpu1(void) { /* Set the Initial Secure Reset Vector Register for CPU 1 */ *(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) = - (uint32_t)_vector_start + - CPU1_FLASH_ADDRESS - - CPU1_FLASH_OFFSET; + (uint32_t)_vector_start + CPU1_FLASH_ADDRESS - CPU1_FLASH_OFFSET; /* Set the CPU Boot wait control after reset */ *(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0; diff --git a/soc/arm/mps3/CMakeLists.txt b/soc/arm/mps3/CMakeLists.txt index 3cf33caa58d..bd8fb92d780 100644 --- a/soc/arm/mps3/CMakeLists.txt +++ b/soc/arm/mps3/CMakeLists.txt @@ -1,10 +1,6 @@ # Copyright (c) 2021 Linaro Limited # SPDX-License-Identifier: Apache-2.0 -zephyr_sources( - soc.c - ) - zephyr_include_directories(.) set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/arm/mps3/soc.c b/soc/arm/mps3/soc.c deleted file mode 100644 index e51a9ba5c59..00000000000 --- a/soc/arm/mps3/soc.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * Copyright (c) 2021 Linaro Limited - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include - - -/* Setup GPIO drivers for accessing FPGAIO registers */ -#define FPGAIO_NODE(n) DT_INST(n, arm_mps3_fpgaio_gpio) -#define FPGAIO_INIT(n) \ - GPIO_MMIO32_INIT(FPGAIO_NODE(n), \ - DT_REG_ADDR(FPGAIO_NODE(n)), \ - BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios))) - -/* We expect there to be 3 arm,mps3-fpgaio-gpio devices: - * led0, button, and misc - */ -FPGAIO_INIT(0); -FPGAIO_INIT(1); -FPGAIO_INIT(2); diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi index 5b1959ff5fe..acd2be8da72 100644 --- a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi +++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi @@ -156,7 +156,7 @@ i2c_shield1: i2c@20d000 { }; gpio_led0: mps2_fpgaio@302000 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302000 0x4>; gpio-controller; @@ -165,16 +165,17 @@ gpio_led0: mps2_fpgaio@302000 { }; gpio_button: mps2_fpgaio@302008 { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x302008 0x4>; gpio-controller; #gpio-cells = <1>; ngpios = <2>; + direction-input; }; gpio_misc: mps2_fpgaio@30204c { - compatible = "arm,mps2-fpgaio-gpio"; + compatible = "arm,mmio32-gpio"; reg = <0x30204c 0x4>; gpio-controller; diff --git a/tests/drivers/gpio/gpio_get_direction/testcase.yaml b/tests/drivers/gpio/gpio_get_direction/testcase.yaml index b66145fc9af..c8dfc105c27 100644 --- a/tests/drivers/gpio/gpio_get_direction/testcase.yaml +++ b/tests/drivers/gpio/gpio_get_direction/testcase.yaml @@ -8,6 +8,5 @@ tests: # Fix exclude when we can exclude just sim run platform_exclude: - mps2/an385 - - mps2/an521/cpu0 - neorv32 filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds")