riscv: better abstraction for register-wide FP load/store opcodes
Same rationale as preceding commit. Let's create pseudo-instructions in
assembly scope to make the code more uniform and readable.
Furthermore the definition of COPY_ESF_FP() was wrong as the width of
floating point registers vary not according to CONFIG_64BIT but
CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION. It is therefore wrong to use
lr/sr (previously RV_OP_LOADREG/RV_OP_STOREREG) and a regular temporary
register to transfer such content.
Note: There are far more efficient ways to copy FP context around but
such optimisations will come separately.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre
Anas Nashif
parent
1fd79b3ef4
commit
bfb7919ed0
3 changed files with 70 additions and 56 deletions
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@ -41,10 +41,10 @@
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op fa7, __z_arch_esf_t_fa7_OFFSET(reg) ;
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#define STORE_FP_CALLER_SAVED(reg) \
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DO_FP_CALLER_SAVED(RV_OP_STOREFPREG, reg)
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DO_FP_CALLER_SAVED(fsr, reg)
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#define LOAD_FP_CALLER_SAVED(reg) \
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DO_FP_CALLER_SAVED(RV_OP_LOADFPREG, reg)
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DO_FP_CALLER_SAVED(flr, reg)
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#define DO_FP_CALLEE_SAVED(op, reg) \
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op fs0, _thread_offset_to_fs0(reg) ;\
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@ -63,58 +63,58 @@
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#define STORE_FP_CALLEE_SAVED(reg) \
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frcsr t2 ;\
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sw t2, _thread_offset_to_fcsr(reg) ;\
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DO_FP_CALLEE_SAVED(RV_OP_STOREFPREG, reg)
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DO_FP_CALLEE_SAVED(fsr, reg)
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#define LOAD_FP_CALLEE_SAVED(reg) \
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lw t2, _thread_offset_to_fcsr(reg) ;\
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fscsr t2 ;\
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DO_FP_CALLEE_SAVED(RV_OP_LOADFPREG, reg)
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DO_FP_CALLEE_SAVED(flr, reg)
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#define COPY_ESF_FP_STATE(to_reg, from_reg, temp) \
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lb temp, __z_arch_esf_t_fp_state_OFFSET(from_reg) ;\
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sb temp, __z_arch_esf_t_fp_state_OFFSET(to_reg) ;
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#define COPY_ESF_FP(to_reg, from_reg, temp) \
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lr temp, __z_arch_esf_t_ft0_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft0_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft1_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft1_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft2_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft2_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft3_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft3_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft4_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft4_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft5_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft5_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft6_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft6_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft7_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft7_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft8_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft8_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft9_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft9_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft10_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft10_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_ft11_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_ft11_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa0_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa0_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa1_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa1_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa2_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa2_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa3_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa3_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa4_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa4_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa5_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa5_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa6_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa6_OFFSET(to_reg) ;\
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lr temp, __z_arch_esf_t_fa7_OFFSET(from_reg) ;\
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sr temp, __z_arch_esf_t_fa7_OFFSET(to_reg) ;
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flr temp, __z_arch_esf_t_ft0_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft0_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft1_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft1_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft2_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft2_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft3_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft3_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft4_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft4_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft5_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft5_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft6_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft6_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft7_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft7_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft8_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft8_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft9_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft9_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft10_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft10_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_ft11_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_ft11_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa0_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa0_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa1_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa1_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa2_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa2_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa3_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa3_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa4_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa4_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa5_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa5_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa6_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa6_OFFSET(to_reg) ;\
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flr temp, __z_arch_esf_t_fa7_OFFSET(from_reg) ;\
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fsr temp, __z_arch_esf_t_fa7_OFFSET(to_reg)
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#define COPY_ESF(to_reg, from_reg, temp) \
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lr temp, __z_arch_esf_t_mepc_OFFSET(from_reg) ;\
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@ -492,7 +492,7 @@ not_user_syscall:
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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lb t1, __z_arch_esf_t_fp_state_OFFSET(t0)
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beqz t1, skip_fp_move_kernel_syscall
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COPY_ESF_FP(sp, t0, t1)
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COPY_ESF_FP(sp, t0, ft0)
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skip_fp_move_kernel_syscall:
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COPY_ESF_FP_STATE(sp, t0, t1)
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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@ -565,7 +565,7 @@ is_user_syscall:
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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lb t1, __z_arch_esf_t_fp_state_OFFSET(t0)
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beqz t1, skip_fp_copy_user_syscall
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COPY_ESF_FP(sp, t0, t1)
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COPY_ESF_FP(sp, t0, ft0)
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skip_fp_copy_user_syscall:
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COPY_ESF_FP_STATE(sp, t0, t1)
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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@ -639,7 +639,7 @@ no_reschedule_user_fault:
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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lb t1, __z_arch_esf_t_fp_state_OFFSET(t0)
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beqz t1, skip_fp_copy_return_user_syscall
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COPY_ESF_FP(sp, t0, t1)
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COPY_ESF_FP(sp, t0, ft0)
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skip_fp_copy_return_user_syscall:
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COPY_ESF_FP_STATE(sp, t0, t1)
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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@ -788,7 +788,7 @@ on_thread_stack:
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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lb t1, __z_arch_esf_t_fp_state_OFFSET(t0)
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beqz t1, skip_fp_move_irq
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COPY_ESF_FP(sp, t0, t1)
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COPY_ESF_FP(sp, t0, ft0)
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skip_fp_move_irq:
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COPY_ESF_FP_STATE(sp, t0, t1)
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#endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
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