michaelh/zephyr
1
0
Fork 0
Code Releases Activity

arch: convert to using newly introduced integer sized types

Browse source 
Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-20 13:30:33 -05:00
commit bf53ebf2c8
85 changed files with 965 additions and 966 deletions
Download patch file Download diff file Expand all files Collapse all files

30
arch/arm/soc/nordic_nrf5/nrf51/soc.c
View file

@ -36,7 +36,7 @@ uint32_t SystemCoreClock __used = __SYSTEM_CLOCK;
static int nordicsemi_nrf51_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);
@ -57,8 +57,8 @@ static int nordicsemi_nrf51_init(struct device *arg)
* will not be available.
*/
if (ftpan_26()) {
*(volatile uint32_t *)0x40000504 = 0xC007FFDF;
*(volatile uint32_t *)0x40006C18 = 0x00008000;
*(volatile u32_t *)0x40000504 = 0xC007FFDF;
*(volatile u32_t *)0x40006C18 = 0x00008000;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59
@ -84,18 +84,18 @@ static int nordicsemi_nrf51_init(struct device *arg)
static bool ftpan_26(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x00) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x10) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -105,10 +105,10 @@ static bool ftpan_26(void)
static bool ftpan_59(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}

58
arch/arm/soc/nordic_nrf5/nrf52/soc.c
View file

@ -32,10 +32,10 @@ extern void _NmiInit(void);
#ifdef CONFIG_SOC_NRF52832
static bool ftpan_32(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -45,10 +45,10 @@ static bool ftpan_32(void)
static bool ftpan_37(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -58,10 +58,10 @@ static bool ftpan_37(void)
static bool ftpan_36(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -84,7 +84,7 @@ static void nordicsemi_nrf52832_init(void)
* for your device located at https://www.nordicsemi.com/
*/
if (ftpan_37()) {
*(volatile uint32_t *)0x400005A0 = 0x3;
*(volatile u32_t *)0x400005A0 = 0x3;
}
/* Workaround for FTPAN-36 "CLOCK: Some registers are not
@ -152,8 +152,8 @@ static void nordicsemi_nrf52832_init(void)
#ifdef CONFIG_SOC_NRF52840
static bool errata_36(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -163,8 +163,8 @@ static bool errata_36(void)
static bool errata_98(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -174,8 +174,8 @@ static bool errata_98(void)
static bool errata_103(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -185,8 +185,8 @@ static bool errata_103(void)
static bool errata_115(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -196,8 +196,8 @@ static bool errata_115(void)
static bool errata_120(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -221,7 +221,7 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_98()) {
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
*(volatile u32_t *)0x4000568Cul = 0x00038148ul;
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM
@ -238,9 +238,9 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_115()) {
*(volatile uint32_t *)0x40000EE4 =
(*(volatile uint32_t *) 0x40000EE4 & 0xFFFFFFF0) |
(*(uint32_t *)0x10000258 & 0x0000000F);
*(volatile u32_t *)0x40000EE4 =
(*(volatile u32_t *) 0x40000EE4 & 0xFFFFFFF0) |
(*(u32_t *)0x10000258 & 0x0000000F);
}
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted"
@ -248,7 +248,7 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_120()) {
*(volatile uint32_t *)0x40029640ul = 0x200ul;
*(volatile u32_t *)0x40029640ul = 0x200ul;
}
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities
@ -329,7 +329,7 @@ static void clock_init(void)
static int nordicsemi_nrf52_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);