arch: convert to using newly introduced integer sized types

Convert code to use u{8,16,32,64}_t and s{8,16,32,64}_t instead of C99
integer types.  There are few places we dont convert over to the new
types because of compatiability with ext/HALs or for ease of transition
at this point.  Fixup a few of the PRI formatters so we build with newlib.

Jira: ZEP-2051

Change-Id: I7d2d3697cad04f20aaa8f6e77228f502cd9c8286
Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2017-04-20 13:30:33 -05:00
commit bf53ebf2c8
85 changed files with 965 additions and 966 deletions

View file

@ -32,7 +32,7 @@
*/
static int arm_beetle_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -15,99 +15,99 @@
/* System Control Register (SYSCON) */
struct syscon {
/* Offset: 0x000 (r/w) remap control register */
volatile uint32_t remap;
volatile u32_t remap;
/* Offset: 0x004 (r/w) pmu control register */
volatile uint32_t pmuctrl;
volatile u32_t pmuctrl;
/* Offset: 0x008 (r/w) reset option register */
volatile uint32_t resetop;
volatile u32_t resetop;
/* Offset: 0x00c (r/w) emi control register */
volatile uint32_t emictrl;
volatile u32_t emictrl;
/* Offset: 0x010 (r/w) reset information register */
volatile uint32_t rstinfo;
volatile uint32_t reserved0[3];
volatile u32_t rstinfo;
volatile u32_t reserved0[3];
/* Offset: 0x020 (r/w)AHB peripheral access control set */
volatile uint32_t ahbper0set;
volatile u32_t ahbper0set;
/* Offset: 0x024 (r/w)AHB peripheral access control clear */
volatile uint32_t ahbper0clr;
volatile uint32_t reserved1[2];
volatile u32_t ahbper0clr;
volatile u32_t reserved1[2];
/* Offset: 0x030 (r/w)APB peripheral access control set */
volatile uint32_t apbper0set;
volatile u32_t apbper0set;
/* Offset: 0x034 (r/w)APB peripheral access control clear */
volatile uint32_t apbper0clr;
volatile uint32_t reserved2[2];
volatile u32_t apbper0clr;
volatile u32_t reserved2[2];
/* Offset: 0x040 (r/w) main clock control register */
volatile uint32_t mainclk;
volatile u32_t mainclk;
/* Offset: 0x044 (r/w) auxiliary / rtc control register */
volatile uint32_t auxclk;
volatile u32_t auxclk;
/* Offset: 0x048 (r/w) pll control register */
volatile uint32_t pllctrl;
volatile u32_t pllctrl;
/* Offset: 0x04c (r/w) pll status register */
volatile uint32_t pllstatus;
volatile u32_t pllstatus;
/* Offset: 0x050 (r/w) sleep control register */
volatile uint32_t sleepcfg;
volatile u32_t sleepcfg;
/* Offset: 0x054 (r/w) flash auxiliary settings control register */
volatile uint32_t flashauxcfg;
volatile uint32_t reserved3[10];
volatile u32_t flashauxcfg;
volatile u32_t reserved3[10];
/* Offset: 0x080 (r/w) AHB peripheral clock set in active state */
volatile uint32_t ahbclkcfg0set;
volatile u32_t ahbclkcfg0set;
/* Offset: 0x084 (r/w) AHB peripheral clock clear in active state */
volatile uint32_t ahbclkcfg0clr;
volatile u32_t ahbclkcfg0clr;
/* Offset: 0x088 (r/w) AHB peripheral clock set in sleep state */
volatile uint32_t ahbclkcfg1set;
volatile u32_t ahbclkcfg1set;
/* Offset: 0x08c (r/w) AHB peripheral clock clear in sleep state */
volatile uint32_t ahbclkcfg1clr;
volatile u32_t ahbclkcfg1clr;
/* Offset: 0x090 (r/w) AHB peripheral clock set in deep sleep state */
volatile uint32_t ahbclkcfg2set;
volatile u32_t ahbclkcfg2set;
/* Offset: 0x094 (r/w) AHB peripheral clock clear in deep sleep state */
volatile uint32_t ahbclkcfg2clr;
volatile uint32_t reserved4[2];
volatile u32_t ahbclkcfg2clr;
volatile u32_t reserved4[2];
/* Offset: 0x0a0 (r/w) APB peripheral clock set in active state */
volatile uint32_t apbclkcfg0set;
volatile u32_t apbclkcfg0set;
/* Offset: 0x0a4 (r/w) APB peripheral clock clear in active state */
volatile uint32_t apbclkcfg0clr;
volatile u32_t apbclkcfg0clr;
/* Offset: 0x0a8 (r/w) APB peripheral clock set in sleep state */
volatile uint32_t apbclkcfg1set;
volatile u32_t apbclkcfg1set;
/* Offset: 0x0ac (r/w) APB peripheral clock clear in sleep state */
volatile uint32_t apbclkcfg1clr;
volatile u32_t apbclkcfg1clr;
/* Offset: 0x0b0 (r/w) APB peripheral clock set in deep sleep state */
volatile uint32_t apbclkcfg2set;
volatile u32_t apbclkcfg2set;
/* Offset: 0x0b4 (r/w) APB peripheral clock clear in deep sleep state */
volatile uint32_t apbclkcfg2clr;
volatile uint32_t reserved5[2];
volatile u32_t apbclkcfg2clr;
volatile u32_t reserved5[2];
/* Offset: 0x0c0 (r/w) AHB peripheral reset select set */
volatile uint32_t ahbprst0set;
volatile u32_t ahbprst0set;
/* Offset: 0x0c4 (r/w) AHB peripheral reset select clear */
volatile uint32_t ahbprst0clr;
volatile u32_t ahbprst0clr;
/* Offset: 0x0c8 (r/w) APB peripheral reset select set */
volatile uint32_t apbprst0set;
volatile u32_t apbprst0set;
/* Offset: 0x0cc (r/w) APB peripheral reset select clear */
volatile uint32_t apbprst0clr;
volatile u32_t apbprst0clr;
/* Offset: 0x0d0 (r/w) AHB power down sleep wakeup source set */
volatile uint32_t pwrdncfg0set;
volatile u32_t pwrdncfg0set;
/* Offset: 0x0d4 (r/w) AHB power down sleep wakeup source clear */
volatile uint32_t pwrdncfg0clr;
volatile u32_t pwrdncfg0clr;
/* Offset: 0x0d8 (r/w) APB power down sleep wakeup source set */
volatile uint32_t pwrdncfg1set;
volatile u32_t pwrdncfg1set;
/* Offset: 0x0dc (r/w) APB power down sleep wakeup source clear */
volatile uint32_t pwrdncfg1clr;
volatile u32_t pwrdncfg1clr;
/* Offset: 0x0e0 ( /w) rtc reset */
volatile uint32_t rtcreset;
volatile u32_t rtcreset;
/* Offset: 0x0e4 (r/w) event interface control register */
volatile uint32_t eventcfg;
volatile uint32_t reserved6[2];
volatile u32_t eventcfg;
volatile u32_t reserved6[2];
/* Offset: 0x0f0 (r/w) sram power control overide */
volatile uint32_t pwrovride0;
volatile u32_t pwrovride0;
/* Offset: 0x0f4 (r/w) embedded flash power control overide */
volatile uint32_t pwrovride1;
volatile u32_t pwrovride1;
/* Offset: 0x0f8 (r/ ) memory status register */
volatile uint32_t memorystatus;
volatile uint32_t reserved7[1];
volatile u32_t memorystatus;
volatile u32_t reserved7[1];
/* Offset: 0x100 (r/w) io pad settings */
volatile uint32_t gpiopadcfg0;
volatile u32_t gpiopadcfg0;
/* Offset: 0x104 (r/w) io pad settings */
volatile uint32_t gpiopadcfg1;
volatile u32_t gpiopadcfg1;
/* Offset: 0x108 (r/w) testmode boot bypass */
volatile uint32_t testmodecfg;
volatile u32_t testmodecfg;
};
#endif /* _ARM_BEETLE_SOC_REGS_H_ */

View file

@ -18,41 +18,41 @@
/* System Control Register (SYSCON) */
struct mps2_syscon {
/* Offset: 0x000 (r/w) remap control register */
volatile uint32_t remap;
volatile u32_t remap;
/* Offset: 0x004 (r/w) pmu control register */
volatile uint32_t pmuctrl;
volatile u32_t pmuctrl;
/* Offset: 0x008 (r/w) reset option register */
volatile uint32_t resetop;
volatile u32_t resetop;
/* Offset: 0x00c (r/w) emi control register */
volatile uint32_t emictrl;
volatile u32_t emictrl;
/* Offset: 0x010 (r/w) reset information register */
volatile uint32_t rstinfo;
volatile u32_t rstinfo;
};
/* Registers in the FPGA system control block */
struct mps2_fpgaio {
/* Offset: 0x000 LED connections */
volatile uint32_t led0;
volatile u32_t led0;
/* Offset: 0x004 RESERVED */
volatile uint32_t reserved1;
volatile u32_t reserved1;
/* Offset: 0x008 Buttons */
volatile uint32_t button;
volatile u32_t button;
/* Offset: 0x00c RESERVED */
volatile uint32_t reserved2;
volatile u32_t reserved2;
/* Offset: 0x010 1Hz up counter */
volatile uint32_t clk1hz;
volatile u32_t clk1hz;
/* Offset: 0x014 100Hz up counter */
volatile uint32_t clk100hz;
volatile u32_t clk100hz;
/* Offset: 0x018 Cycle up counter */
volatile uint32_t counter;
volatile u32_t counter;
/* Offset: 0x01c Reload value for prescale counter */
volatile uint32_t prescale;
volatile u32_t prescale;
/* Offset: 0x020 32-bit Prescale counter */
volatile uint32_t pscntr;
volatile u32_t pscntr;
/* Offset: 0x024 RESERVED */
volatile uint32_t reserved3[10];
volatile u32_t reserved3[10];
/* Offset: 0x04c Misc control */
volatile uint32_t misc;
volatile u32_t misc;
};
/* Defines for bits in fpgaio led0 register */

View file

@ -11,7 +11,7 @@
#include <misc/__assert.h>
#include "soc_gpio.h"
static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags)
static void configure_common_attr(Pio *pio, u32_t mask, u32_t flags)
{
/* Disable interrupts on the pin(s) */
pio->PIO_IDR = mask;
@ -38,7 +38,7 @@ static void configure_common_attr(Pio *pio, uint32_t mask, uint32_t flags)
}
}
static void configure_input_attr(Pio *pio, uint32_t mask, uint32_t flags)
static void configure_input_attr(Pio *pio, u32_t mask, u32_t flags)
{
/* Configure input filter */
if ((flags & SOC_GPIO_IN_FILTER_MASK) != 0) {
@ -86,7 +86,7 @@ static void configure_input_attr(Pio *pio, uint32_t mask, uint32_t flags)
}
}
static void configure_output_attr(Pio *pio, uint32_t mask, uint32_t flags)
static void configure_output_attr(Pio *pio, u32_t mask, u32_t flags)
{
/* Enable control of the I/O line by the PIO_ODSR register */
pio->PIO_OWER = mask;
@ -94,11 +94,11 @@ static void configure_output_attr(Pio *pio, uint32_t mask, uint32_t flags)
void soc_gpio_configure(const struct soc_gpio_pin *pin)
{
uint32_t mask = pin->mask;
u32_t mask = pin->mask;
Pio *pio = pin->regs;
uint8_t periph_id = pin->periph_id;
uint32_t flags = pin->flags;
uint32_t type = pin->flags & SOC_GPIO_FUNC_MASK;
u8_t periph_id = pin->periph_id;
u32_t flags = pin->flags;
u32_t type = pin->flags & SOC_GPIO_FUNC_MASK;
/* Configure pin attributes common to all functions */
configure_common_attr(pio, mask, flags);

View file

@ -70,10 +70,10 @@
#define SOC_GPIO_FUNC_OUT_1 (6 << SOC_GPIO_FUNC_POS)
struct soc_gpio_pin {
uint32_t mask; /** pin(s) bit mask */
u32_t mask; /** pin(s) bit mask */
Pio *regs; /** pointer to registers of the PIO controller */
uint8_t periph_id; /** peripheral ID of the PIO controller */
uint32_t flags; /** pin flags/attributes */
u8_t periph_id; /** peripheral ID of the PIO controller */
u32_t flags; /** pin flags/attributes */
};
/**
@ -148,7 +148,7 @@ static inline void soc_gpio_clear(const struct soc_gpio_pin *pin)
* @return pin(s) value. To assess value of a specific pin the pin's bit
* field has to be read.
*/
static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin)
static inline u32_t soc_gpio_get(const struct soc_gpio_pin *pin)
{
return pin->regs->PIO_PDSR & pin->mask;
}
@ -173,7 +173,7 @@ static inline uint32_t soc_gpio_get(const struct soc_gpio_pin *pin)
* @param div slow clock divider, valid values: from 0 to 2^14 - 1
*/
static inline void soc_gpio_debounce_length_set(const struct soc_gpio_pin *pin,
uint32_t div)
u32_t div)
{
pin->regs->PIO_SCDR = PIO_SCDR_DIV(div);
}

View file

@ -16,7 +16,7 @@
#error "Unsupported SoC, update soc_pmc.c functions"
#endif
void soc_pmc_peripheral_enable(uint32_t id)
void soc_pmc_peripheral_enable(u32_t id)
{
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");
@ -29,7 +29,7 @@ void soc_pmc_peripheral_enable(uint32_t id)
}
}
void soc_pmc_peripheral_disable(uint32_t id)
void soc_pmc_peripheral_disable(u32_t id)
{
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");
@ -42,7 +42,7 @@ void soc_pmc_peripheral_disable(uint32_t id)
}
}
uint32_t soc_pmc_peripheral_is_enabled(uint32_t id)
u32_t soc_pmc_peripheral_is_enabled(u32_t id)
{
__ASSERT(id < ID_PERIPH_COUNT, "Invalid peripheral id");

View file

@ -18,14 +18,14 @@
*
* @param id peripheral module id, as defined in data sheet.
*/
void soc_pmc_peripheral_enable(uint32_t id);
void soc_pmc_peripheral_enable(u32_t id);
/**
* @brief Disable the clock of specified peripheral module.
*
* @param id peripheral module id, as defined in data sheet.
*/
void soc_pmc_peripheral_disable(uint32_t id);
void soc_pmc_peripheral_disable(u32_t id);
/**
* @brief Check if specified peripheral module is enabled.
@ -33,6 +33,6 @@ void soc_pmc_peripheral_disable(uint32_t id);
* @param id peripheral module id, as defined in data sheet.
* @return 1 if peripheral is enabled, 0 otherwise
*/
uint32_t soc_pmc_peripheral_is_enabled(uint32_t id);
u32_t soc_pmc_peripheral_is_enabled(u32_t id);
#endif /* _ATMEL_SAM_SOC_PMC_H_ */

View file

@ -53,7 +53,7 @@
*/
static ALWAYS_INLINE void clock_init(void)
{
uint32_t reg_val;
u32_t reg_val;
#ifdef CONFIG_SOC_ATMEL_SAME70_EXT_SLCK
/* Switch slow clock to the external 32 kHz crystal oscillator */
@ -217,7 +217,7 @@ static ALWAYS_INLINE void clock_init(void)
*/
static int atmel_same70_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -31,7 +31,7 @@
*/
static ALWAYS_INLINE void clock_init(void)
{
uint32_t tmp;
u32_t tmp;
/* Note:
* Magic numbers below are obtained by reading the registers
@ -141,7 +141,7 @@ static ALWAYS_INLINE void clock_init(void)
*/
static int atmel_sam3_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -21,215 +21,215 @@
* Starts at offset 0x100.
*/
struct __pdc {
uint32_t rpr; /* 0x100 Receive Pointer */
uint32_t rcr; /* 0x104 Receive Counter */
uint32_t tpr; /* 0x108 Transmit Pointer */
uint32_t tcr; /* 0x10C Transmit Counter */
uint32_t rnpr; /* 0x110 Receive Next Pointer */
uint32_t rncr; /* 0x114 Receive Next Counter */
uint32_t tnpr; /* 0x118 Transmit Next Pointer */
uint32_t tncr; /* 0x11C Transmit Next Counter */
uint32_t ptcr; /* 0x120 Transfer Control */
uint32_t ptsr; /* 0x124 Transfer Status */
u32_t rpr; /* 0x100 Receive Pointer */
u32_t rcr; /* 0x104 Receive Counter */
u32_t tpr; /* 0x108 Transmit Pointer */
u32_t tcr; /* 0x10C Transmit Counter */
u32_t rnpr; /* 0x110 Receive Next Pointer */
u32_t rncr; /* 0x114 Receive Next Counter */
u32_t tnpr; /* 0x118 Transmit Next Pointer */
u32_t tncr; /* 0x11C Transmit Next Counter */
u32_t ptcr; /* 0x120 Transfer Control */
u32_t ptsr; /* 0x124 Transfer Status */
};
/* Enhanced Embedded Flash Controller */
struct __eefc {
uint32_t fmr; /* 0x00 Flash Mode Register */
uint32_t fcr; /* 0x04 Flash Command Register */
uint32_t fsr; /* 0x08 Flash Status Register */
uint32_t frr; /* 0x0C Flash Result Register */
u32_t fmr; /* 0x00 Flash Mode Register */
u32_t fcr; /* 0x04 Flash Command Register */
u32_t fsr; /* 0x08 Flash Status Register */
u32_t frr; /* 0x0C Flash Result Register */
};
/* PIO Controller */
struct __pio {
uint32_t per; /* 0x00 Enable */
uint32_t pdr; /* 0x04 Disable */
uint32_t psr; /* 0x08 Status */
u32_t per; /* 0x00 Enable */
u32_t pdr; /* 0x04 Disable */
u32_t psr; /* 0x08 Status */
uint32_t res0; /* 0x0C reserved */
u32_t res0; /* 0x0C reserved */
uint32_t oer; /* 0x10 Output Enable */
uint32_t odr; /* 0x14 Output Disable */
uint32_t osr; /* 0x18 Output Status */
u32_t oer; /* 0x10 Output Enable */
u32_t odr; /* 0x14 Output Disable */
u32_t osr; /* 0x18 Output Status */
uint32_t res1; /* 0x1C reserved */
u32_t res1; /* 0x1C reserved */
uint32_t ifer; /* 0x20 Glitch Input Filter Enable */
uint32_t ifdr; /* 0x24 Glitch Input Filter Disable */
uint32_t ifsr; /* 0x28 Glitch Input Fitler Status */
u32_t ifer; /* 0x20 Glitch Input Filter Enable */
u32_t ifdr; /* 0x24 Glitch Input Filter Disable */
u32_t ifsr; /* 0x28 Glitch Input Fitler Status */
uint32_t res2; /* 0x2C reserved */
u32_t res2; /* 0x2C reserved */
uint32_t sodr; /* 0x30 Set Output Data */
uint32_t codr; /* 0x34 Clear Output Data */
uint32_t odsr; /* 0x38 Output Data Status */
uint32_t pdsr; /* 0x3C Pin Data Status */
u32_t sodr; /* 0x30 Set Output Data */
u32_t codr; /* 0x34 Clear Output Data */
u32_t odsr; /* 0x38 Output Data Status */
u32_t pdsr; /* 0x3C Pin Data Status */
uint32_t ier; /* 0x40 Interrupt Enable */
uint32_t idr; /* 0x44 Interrupt Disable */
uint32_t imr; /* 0x48 Interrupt Mask */
uint32_t isr; /* 0x4C Interrupt Status */
u32_t ier; /* 0x40 Interrupt Enable */
u32_t idr; /* 0x44 Interrupt Disable */
u32_t imr; /* 0x48 Interrupt Mask */
u32_t isr; /* 0x4C Interrupt Status */
uint32_t mder; /* 0x50 Multi-driver Enable */
uint32_t mddr; /* 0x54 Multi-driver Disable */
uint32_t mdsr; /* 0x58 Multi-driver Status */
u32_t mder; /* 0x50 Multi-driver Enable */
u32_t mddr; /* 0x54 Multi-driver Disable */
u32_t mdsr; /* 0x58 Multi-driver Status */
uint32_t res3; /* 0x5C reserved */
u32_t res3; /* 0x5C reserved */
uint32_t pudr; /* 0x60 Pull-up Disable */
uint32_t puer; /* 0x64 Pull-up Enable */
uint32_t pusr; /* 0x68 Pad Pull-up Status */
u32_t pudr; /* 0x60 Pull-up Disable */
u32_t puer; /* 0x64 Pull-up Enable */
u32_t pusr; /* 0x68 Pad Pull-up Status */
uint32_t res4; /* 0x6C reserved */
u32_t res4; /* 0x6C reserved */
uint32_t absr; /* 0x70 Peripheral AB Select */
u32_t absr; /* 0x70 Peripheral AB Select */
uint32_t res5[3]; /* 0x74-0x7C reserved */
u32_t res5[3]; /* 0x74-0x7C reserved */
uint32_t scifsr; /* 0x80 System Clock Glitch Input */
u32_t scifsr; /* 0x80 System Clock Glitch Input */
/* Filter Select */
uint32_t difsr; /* 0x84 Debouncing Input Filter */
u32_t difsr; /* 0x84 Debouncing Input Filter */
/* Select */
uint32_t ifdgsr; /* 0x88 Glitch or Debouncing Input */
u32_t ifdgsr; /* 0x88 Glitch or Debouncing Input */
/* Filter Clock Selection */
/* Status */
uint32_t scdr; /* 0x8C Slow Clock Divider Debounce */
u32_t scdr; /* 0x8C Slow Clock Divider Debounce */
uint32_t res6[4]; /* 0x90-0x9C reserved */
u32_t res6[4]; /* 0x90-0x9C reserved */
uint32_t ower; /* 0xA0 Output Write Enable */
uint32_t owdr; /* 0xA4 Output Write Disable */
uint32_t owsr; /* 0xA8 Output Write Status */
u32_t ower; /* 0xA0 Output Write Enable */
u32_t owdr; /* 0xA4 Output Write Disable */
u32_t owsr; /* 0xA8 Output Write Status */
uint32_t res7; /* 0xAC reserved */
u32_t res7; /* 0xAC reserved */
uint32_t aimer; /* 0xB0 Additional Interrupt Modes */
u32_t aimer; /* 0xB0 Additional Interrupt Modes */
/* Enable */
uint32_t aimdr; /* 0xB4 Additional Interrupt Modes */
u32_t aimdr; /* 0xB4 Additional Interrupt Modes */
/* Disable */
uint32_t aimmr; /* 0xB8 Additional Interrupt Modes */
u32_t aimmr; /* 0xB8 Additional Interrupt Modes */
/* Mask */
uint32_t res8; /* 0xBC reserved */
u32_t res8; /* 0xBC reserved */
uint32_t esr; /* 0xC0 Edge Select */
uint32_t lsr; /* 0xC4 Level Select */
uint32_t elsr; /* 0xC8 Edge/Level Status */
u32_t esr; /* 0xC0 Edge Select */
u32_t lsr; /* 0xC4 Level Select */
u32_t elsr; /* 0xC8 Edge/Level Status */
uint32_t res9; /* 0xCC reserved */
u32_t res9; /* 0xCC reserved */
uint32_t fellsr; /* 0xD0 Falling Edge/Low Level Sel */
uint32_t rehlsr; /* 0xD4 Rising Edge/High Level Sel */
uint32_t frlhsr; /* 0xD8 Fall/Rise - Low/High Status */
u32_t fellsr; /* 0xD0 Falling Edge/Low Level Sel */
u32_t rehlsr; /* 0xD4 Rising Edge/High Level Sel */
u32_t frlhsr; /* 0xD8 Fall/Rise - Low/High Status */
uint32_t res10; /* 0xDC reserved */
u32_t res10; /* 0xDC reserved */
uint32_t locksr; /* 0xE0 Lock Status */
u32_t locksr; /* 0xE0 Lock Status */
uint32_t wpmr; /* 0xE4 Write Protect Mode */
uint32_t wpsr; /* 0xE8 Write Protect Status */
u32_t wpmr; /* 0xE4 Write Protect Mode */
u32_t wpsr; /* 0xE8 Write Protect Status */
};
/* Power Management Controller */
struct __pmc {
uint32_t scer; /* 0x00 System Clock Enable */
uint32_t scdr; /* 0x04 System Clock Disable */
uint32_t scsr; /* 0x08 System Clock Status */
u32_t scer; /* 0x00 System Clock Enable */
u32_t scdr; /* 0x04 System Clock Disable */
u32_t scsr; /* 0x08 System Clock Status */
uint32_t res0; /* 0x0C reserved */
u32_t res0; /* 0x0C reserved */
uint32_t pcer0; /* 0x10 Peripheral Clock Enable 0 */
uint32_t pcdr0; /* 0x14 Peripheral Clock Disable 0 */
uint32_t pcsr0; /* 0x18 Peripheral Clock Status 0 */
u32_t pcer0; /* 0x10 Peripheral Clock Enable 0 */
u32_t pcdr0; /* 0x14 Peripheral Clock Disable 0 */
u32_t pcsr0; /* 0x18 Peripheral Clock Status 0 */
uint32_t ckgr_uckr; /* 0x1C UTMI Clock */
uint32_t ckgr_mor; /* 0x20 Main Oscillator */
uint32_t ckgr_mcfr; /* 0x24 Main Clock Freq. */
uint32_t ckgr_pllar; /* 0x28 PLLA */
u32_t ckgr_uckr; /* 0x1C UTMI Clock */
u32_t ckgr_mor; /* 0x20 Main Oscillator */
u32_t ckgr_mcfr; /* 0x24 Main Clock Freq. */
u32_t ckgr_pllar; /* 0x28 PLLA */
uint32_t res1; /* 0x2C reserved */
u32_t res1; /* 0x2C reserved */
uint32_t mckr; /* 0x30 Master Clock */
u32_t mckr; /* 0x30 Master Clock */
uint32_t res2; /* 0x34 reserved */
u32_t res2; /* 0x34 reserved */
uint32_t usb; /* 0x38 USB Clock */
u32_t usb; /* 0x38 USB Clock */
uint32_t res3; /* 0x3C reserved */
u32_t res3; /* 0x3C reserved */
uint32_t pck0; /* 0x40 Programmable Clock 0 */
uint32_t pck1; /* 0x44 Programmable Clock 1 */
uint32_t pck2; /* 0x48 Programmable Clock 2 */
u32_t pck0; /* 0x40 Programmable Clock 0 */
u32_t pck1; /* 0x44 Programmable Clock 1 */
u32_t pck2; /* 0x48 Programmable Clock 2 */
uint32_t res4[5]; /* 0x4C-0x5C reserved */
u32_t res4[5]; /* 0x4C-0x5C reserved */
uint32_t ier; /* 0x60 Interrupt Enable */
uint32_t idr; /* 0x64 Interrupt Disable */
uint32_t sr; /* 0x68 Status */
uint32_t imr; /* 0x6C Interrupt Mask */
u32_t ier; /* 0x60 Interrupt Enable */
u32_t idr; /* 0x64 Interrupt Disable */
u32_t sr; /* 0x68 Status */
u32_t imr; /* 0x6C Interrupt Mask */
uint32_t fsmr; /* 0x70 Fast Startup Mode */
uint32_t fspr; /* 0x74 Fast Startup Polarity */
u32_t fsmr; /* 0x70 Fast Startup Mode */
u32_t fspr; /* 0x74 Fast Startup Polarity */
uint32_t focr; /* 0x78 Fault Outpu Clear */
u32_t focr; /* 0x78 Fault Outpu Clear */
uint32_t res5[26]; /* 0x7C-0xE0 reserved */
u32_t res5[26]; /* 0x7C-0xE0 reserved */
uint32_t wpmr; /* 0xE4 Write Protect Mode */
uint32_t wpsr; /* 0xE8 Write Protect Status */
u32_t wpmr; /* 0xE4 Write Protect Mode */
u32_t wpsr; /* 0xE8 Write Protect Status */
uint32_t res6[5]; /* 0xEC-0xFC reserved */
u32_t res6[5]; /* 0xEC-0xFC reserved */
uint32_t pcer1; /* 0x100 Peripheral Clock Enable 1 */
uint32_t pcdr1; /* 0x104 Peripheral Clock Disable 1 */
uint32_t pcsr1; /* 0x108 Peripheral Clock Status 1 */
u32_t pcer1; /* 0x100 Peripheral Clock Enable 1 */
u32_t pcdr1; /* 0x104 Peripheral Clock Disable 1 */
u32_t pcsr1; /* 0x108 Peripheral Clock Status 1 */
uint32_t pcr; /* 0x10C Peripheral Control */
u32_t pcr; /* 0x10C Peripheral Control */
};
/* Supply Controller (SUPC) */
struct __supc {
uint32_t cr; /* 0x00 Control */
uint32_t smmr; /* 0x04 Supply Monitor Mode */
uint32_t mr; /* 0x08 Mode */
uint32_t wumr; /* 0x0C Wake Up Mode */
uint32_t wuir; /* 0x10 Wake Up Inputs */
uint32_t sr; /* 0x14 Status */
u32_t cr; /* 0x00 Control */
u32_t smmr; /* 0x04 Supply Monitor Mode */
u32_t mr; /* 0x08 Mode */
u32_t wumr; /* 0x0C Wake Up Mode */
u32_t wuir; /* 0x10 Wake Up Inputs */
u32_t sr; /* 0x14 Status */
};
/* Two-wire Interface (TWI), aka I2C */
struct __twi {
uint32_t cr; /* 0x00 Control */
uint32_t mmr; /* 0x04 Master Mode */
uint32_t smr; /* 0x08 Slave Mode */
uint32_t iadr; /* 0x0C Internal Address */
uint32_t cwgr; /* 0x10 Clock Waveform Generator */
u32_t cr; /* 0x00 Control */
u32_t mmr; /* 0x04 Master Mode */
u32_t smr; /* 0x08 Slave Mode */
u32_t iadr; /* 0x0C Internal Address */
u32_t cwgr; /* 0x10 Clock Waveform Generator */
uint32_t rev0[3]; /* 0x14-0x1C reserved */
u32_t rev0[3]; /* 0x14-0x1C reserved */
uint32_t sr; /* 0x20 Status */
u32_t sr; /* 0x20 Status */
uint32_t ier; /* 0x24 Interrupt Enable */
uint32_t idr; /* 0x28 Interrupt Disable */
uint32_t imr; /* 0x2C Interrupt Mask */
u32_t ier; /* 0x24 Interrupt Enable */
u32_t idr; /* 0x28 Interrupt Disable */
u32_t imr; /* 0x2C Interrupt Mask */
uint32_t rhr; /* 0x30 Receive Holding */
uint32_t thr; /* 0x34 Transmit Holding */
u32_t rhr; /* 0x30 Receive Holding */
u32_t thr; /* 0x34 Transmit Holding */
uint32_t rev1[50]; /* 0x38-0xFC Reserved */
u32_t rev1[50]; /* 0x38-0xFC Reserved */
struct __pdc pdc; /* 0x100 - 0x124 PDC */
};
/* Watchdog timer (WDT) */
struct __wdt {
uint32_t cr; /* 0x00 Control Register */
uint32_t mr; /* 0x04 Mode Register */
uint32_t sr; /* 0x08 Status Register */
u32_t cr; /* 0x00 Control Register */
u32_t mr; /* 0x04 Mode Register */
u32_t sr; /* 0x08 Status Register */
};
#endif /* _ATMEL_SAM3_SOC_REGS_H_ */

View file

@ -36,7 +36,7 @@ uint32_t SystemCoreClock __used = __SYSTEM_CLOCK;
static int nordicsemi_nrf51_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);
@ -57,8 +57,8 @@ static int nordicsemi_nrf51_init(struct device *arg)
* will not be available.
*/
if (ftpan_26()) {
*(volatile uint32_t *)0x40000504 = 0xC007FFDF;
*(volatile uint32_t *)0x40006C18 = 0x00008000;
*(volatile u32_t *)0x40000504 = 0xC007FFDF;
*(volatile u32_t *)0x40006C18 = 0x00008000;
}
/* Disable PROTENSET registers under debug, as indicated by PAN 59
@ -84,18 +84,18 @@ static int nordicsemi_nrf51_init(struct device *arg)
static bool ftpan_26(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x00) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x10) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -105,10 +105,10 @@ static bool ftpan_26(void)
static bool ftpan_59(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x1) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x40) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}

View file

@ -32,10 +32,10 @@ extern void _NmiInit(void);
#ifdef CONFIG_SOC_NRF52832
static bool ftpan_32(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -45,10 +45,10 @@ static bool ftpan_32(void)
static bool ftpan_37(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -58,10 +58,10 @@ static bool ftpan_37(void)
static bool ftpan_36(void)
{
if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
if ((((*(u32_t *)0xF0000FE0) & 0x000000FF) == 0x6) &&
(((*(u32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
if ((((*(u32_t *)0xF0000FE8) & 0x000000F0) == 0x30) &&
(((*(u32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
return true;
}
}
@ -84,7 +84,7 @@ static void nordicsemi_nrf52832_init(void)
* for your device located at https://www.nordicsemi.com/
*/
if (ftpan_37()) {
*(volatile uint32_t *)0x400005A0 = 0x3;
*(volatile u32_t *)0x400005A0 = 0x3;
}
/* Workaround for FTPAN-36 "CLOCK: Some registers are not
@ -152,8 +152,8 @@ static void nordicsemi_nrf52832_init(void)
#ifdef CONFIG_SOC_NRF52840
static bool errata_36(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -163,8 +163,8 @@ static bool errata_36(void)
static bool errata_98(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -174,8 +174,8 @@ static bool errata_98(void)
static bool errata_103(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -185,8 +185,8 @@ static bool errata_103(void)
static bool errata_115(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -196,8 +196,8 @@ static bool errata_115(void)
static bool errata_120(void)
{
if ((*(uint32_t *)0x10000130ul == 0x8ul) &&
(*(uint32_t *)0x10000134ul == 0x0ul)) {
if ((*(u32_t *)0x10000130ul == 0x8ul) &&
(*(u32_t *)0x10000134ul == 0x0ul)) {
return true;
}
@ -221,7 +221,7 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_98()) {
*(volatile uint32_t *)0x4000568Cul = 0x00038148ul;
*(volatile u32_t *)0x4000568Cul = 0x00038148ul;
}
/* Workaround for Errata 103 "CCM: Wrong reset value of CCM
@ -238,9 +238,9 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_115()) {
*(volatile uint32_t *)0x40000EE4 =
(*(volatile uint32_t *) 0x40000EE4 & 0xFFFFFFF0) |
(*(uint32_t *)0x10000258 & 0x0000000F);
*(volatile u32_t *)0x40000EE4 =
(*(volatile u32_t *) 0x40000EE4 & 0xFFFFFFF0) |
(*(u32_t *)0x10000258 & 0x0000000F);
}
/* Workaround for Errata 120 "QSPI: Data read or written is corrupted"
@ -248,7 +248,7 @@ static void nordicsemi_nrf52840_init(void)
* https://infocenter.nordicsemi.com/
*/
if (errata_120()) {
*(volatile uint32_t *)0x40029640ul = 0x200ul;
*(volatile u32_t *)0x40029640ul = 0x200ul;
}
/* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities
@ -329,7 +329,7 @@ static void clock_init(void)
static int nordicsemi_nrf52_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -49,7 +49,7 @@
* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
*
*/
uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
@ -153,7 +153,7 @@ static int fsl_frdm_k64f_init(struct device *arg)
ARG_UNUSED(arg);
int oldLevel; /* old interrupt lock level */
uint32_t temp_reg;
u32_t temp_reg;
/* disable interrupts */
oldLevel = irq_lock();

View file

@ -32,7 +32,7 @@
* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
*
*/
uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected

View file

@ -37,7 +37,7 @@
* -Reserved, 1 byte, (EEPROM protection byte for FlexNVM)
*
*/
uint8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
u8_t __kinetis_flash_config_section __kinetis_flash_config[] = {
/* Backdoor Comparison Key (unused) */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
/* Program flash protection; 1 bit/region - 0=protected, 1=unprotected
@ -77,7 +77,7 @@ static const sim_clock_config_t simConfig = {
*/
static void CLOCK_SYS_FllStableDelay(void)
{
uint32_t i = 30000U;
u32_t i = 30000U;
while (i--) {
__NOP();
}

View file

@ -25,27 +25,27 @@ enum {
/* 3.3.3 FLASH_ACR */
union __ef_acr {
uint32_t val;
u32_t val;
struct {
uint32_t latency :3 __packed;
uint32_t hlfcya :1 __packed;
uint32_t prftbe :1 __packed;
uint32_t prftbs :1 __packed;
uint32_t rsvd__6_31 :26 __packed;
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32f10x_flash {
union __ef_acr acr;
uint32_t keyr;
uint32_t optkeyr;
uint32_t sr;
uint32_t cr;
uint32_t ar;
uint32_t rsvd;
uint32_t obr;
uint32_t wrpr;
u32_t keyr;
u32_t optkeyr;
u32_t sr;
u32_t cr;
u32_t ar;
u32_t rsvd;
u32_t obr;
u32_t wrpr;
};
#endif /* _STM32F10X_FLASHREGISTERS_H_ */

View file

@ -20,74 +20,74 @@
/* 9.2 GPIO registers - each GPIO port controls 16 pins */
struct stm32f10x_gpio {
uint32_t crl;
uint32_t crh;
uint32_t idr;
uint32_t odr;
uint32_t bsrr;
uint32_t brr;
uint32_t lckr;
u32_t crl;
u32_t crh;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t brr;
u32_t lckr;
};
/* 9.4.1 AFIO_EVCR */
union __afio_evcr {
uint32_t val;
u32_t val;
struct {
uint32_t pin :4 __packed;
uint32_t port :3 __packed;
uint32_t evoe :1 __packed;
uint32_t rsvd__8_31 :24 __packed;
u32_t pin :4 __packed;
u32_t port :3 __packed;
u32_t evoe :1 __packed;
u32_t rsvd__8_31 :24 __packed;
} bit;
};
/* 9.4.2 AFIO_MAPR */
/* TODO: support connectivity line devices */
union __afio_mapr {
uint32_t val;
u32_t val;
struct {
uint32_t spi1_remap :1 __packed;
uint32_t i2c1_remap :1 __packed;
uint32_t usart1_remap :1 __packed;
uint32_t usart2_remap :1 __packed;
uint32_t usart3_remap :2 __packed;
uint32_t tim1_remap :2 __packed;
uint32_t tim2_remap :2 __packed;
uint32_t tim3_remap :2 __packed;
uint32_t tim4_remap :1 __packed;
uint32_t can_remap :2 __packed;
uint32_t pd01_remap :1 __packed;
uint32_t tim5ch4_iremap :1 __packed;
uint32_t adc1_etrginj_remap :1 __packed;
uint32_t adc1_etrgreg_remap :1 __packed;
uint32_t adc2_etrginj_remap :1 __packed;
uint32_t adc2_etrgreg_remap :1 __packed;
uint32_t rsvd__21_23 :3 __packed;
uint32_t swj_cfg :3 __packed;
uint32_t rsvd__27_31 :5 __packed;
u32_t spi1_remap :1 __packed;
u32_t i2c1_remap :1 __packed;
u32_t usart1_remap :1 __packed;
u32_t usart2_remap :1 __packed;
u32_t usart3_remap :2 __packed;
u32_t tim1_remap :2 __packed;
u32_t tim2_remap :2 __packed;
u32_t tim3_remap :2 __packed;
u32_t tim4_remap :1 __packed;
u32_t can_remap :2 __packed;
u32_t pd01_remap :1 __packed;
u32_t tim5ch4_iremap :1 __packed;
u32_t adc1_etrginj_remap :1 __packed;
u32_t adc1_etrgreg_remap :1 __packed;
u32_t adc2_etrginj_remap :1 __packed;
u32_t adc2_etrgreg_remap :1 __packed;
u32_t rsvd__21_23 :3 __packed;
u32_t swj_cfg :3 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
/* 9.4.{3,4,5,6} AFIO_EXTICRx */
union __afio_exticr {
uint32_t val;
u32_t val;
struct {
uint16_t rsvd__16_31;
uint16_t exti;
u16_t rsvd__16_31;
u16_t exti;
} bit;
};
/* 9.4.7 AFIO_MAPR2 */
union __afio_mapr2 {
uint32_t val;
u32_t val;
struct {
uint32_t rsvd__0_4 :5 __packed;
uint32_t tim9_remap :1 __packed;
uint32_t tim10_remap :1 __packed;
uint32_t tim11_remap :1 __packed;
uint32_t tim13_remap :1 __packed;
uint32_t tim14_remap :1 __packed;
uint32_t fsmc_nadv :1 __packed;
uint32_t rsvd__11_31 :21 __packed;
u32_t rsvd__0_4 :5 __packed;
u32_t tim9_remap :1 __packed;
u32_t tim10_remap :1 __packed;
u32_t tim11_remap :1 __packed;
u32_t tim13_remap :1 __packed;
u32_t tim14_remap :1 __packed;
u32_t fsmc_nadv :1 __packed;
u32_t rsvd__11_31 :21 __packed;
} bit;
};

View file

@ -95,78 +95,78 @@ enum {
*/
union __rcc_cr {
uint32_t val;
u32_t val;
struct {
uint32_t hsion :1 __packed;
uint32_t hsirdy :1 __packed;
uint32_t rsvd__2 :1 __packed;
uint32_t hsitrim :5 __packed;
uint32_t hsical :8 __packed;
uint32_t hseon :1 __packed;
uint32_t hserdy :1 __packed;
uint32_t hsebyp :1 __packed;
uint32_t csson :1 __packed;
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
u32_t hsion :1 __packed;
u32_t hsirdy :1 __packed;
u32_t rsvd__2 :1 __packed;
u32_t hsitrim :5 __packed;
u32_t hsical :8 __packed;
u32_t hseon :1 __packed;
u32_t hserdy :1 __packed;
u32_t hsebyp :1 __packed;
u32_t csson :1 __packed;
u32_t rsvd__20_23 :4 __packed;
u32_t pllon :1 __packed;
u32_t pllrdy :1 __packed;
#if CONFIG_SOC_STM32F10X_DENSITY_DEVICE
uint32_t rsvd__26_31 :6 __packed;
u32_t rsvd__26_31 :6 __packed;
#elif CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
uint32_t pll2on :1 __packed;
uint32_t pll2rdy :1 __packed;
uint32_t pll3on :1 __packed;
uint32_t pll3rdy :1 __packed;
uint32_t rsvd__30_31 :2 __packed;
u32_t pll2on :1 __packed;
u32_t pll2rdy :1 __packed;
u32_t pll3on :1 __packed;
u32_t pll3rdy :1 __packed;
u32_t rsvd__30_31 :2 __packed;
#endif
} bit;
};
union __rcc_cfgr {
uint32_t val;
u32_t val;
struct {
uint32_t sw :2 __packed;
uint32_t sws :2 __packed;
uint32_t hpre :4 __packed;
uint32_t ppre1 :3 __packed;
uint32_t ppre2 :3 __packed;
uint32_t adcpre :2 __packed;
uint32_t pllsrc :1 __packed;
uint32_t pllxtpre :1 __packed;
uint32_t pllmul :4 __packed;
uint32_t usbpre :1 __packed;
uint32_t rsvd__23 :1 __packed;
uint32_t mco :3 __packed;
uint32_t rsvd__27_31 :5 __packed;
u32_t sw :2 __packed;
u32_t sws :2 __packed;
u32_t hpre :4 __packed;
u32_t ppre1 :3 __packed;
u32_t ppre2 :3 __packed;
u32_t adcpre :2 __packed;
u32_t pllsrc :1 __packed;
u32_t pllxtpre :1 __packed;
u32_t pllmul :4 __packed;
u32_t usbpre :1 __packed;
u32_t rsvd__23 :1 __packed;
u32_t mco :3 __packed;
u32_t rsvd__27_31 :5 __packed;
} bit;
};
union __rcc_cfgr2 {
uint32_t val;
u32_t val;
struct {
uint32_t prediv1 :4 __packed;
uint32_t prediv2 :4 __packed;
uint32_t pll2mul :4 __packed;
uint32_t pll3mul :4 __packed;
uint32_t prediv1src :1 __packed;
uint32_t i2s2sr :1 __packed;
uint32_t i2s3sr :1 __packed;
uint32_t rsvd__19_31 :13 __packed;
u32_t prediv1 :4 __packed;
u32_t prediv2 :4 __packed;
u32_t pll2mul :4 __packed;
u32_t pll3mul :4 __packed;
u32_t prediv1src :1 __packed;
u32_t i2s2sr :1 __packed;
u32_t i2s3sr :1 __packed;
u32_t rsvd__19_31 :13 __packed;
} bit;
};
struct stm32f10x_rcc {
union __rcc_cr cr;
union __rcc_cfgr cfgr;
uint32_t cir;
uint32_t apb2rstr;
uint32_t apb1rstr;
uint32_t ahbenr;
uint32_t apb2enr;
uint32_t apb1enr;
uint32_t bdcr;
uint32_t csr;
u32_t cir;
u32_t apb2rstr;
u32_t apb1rstr;
u32_t ahbenr;
u32_t apb2enr;
u32_t apb1enr;
u32_t bdcr;
u32_t csr;
#ifdef CONFIG_SOC_STM32F10X_CONNECTIVITY_LINE_DEVICE
uint32_t ahbrstr;
u32_t ahbrstr;
union __rcc_cfgr2 cfgr2;
#endif
};

View file

@ -37,7 +37,7 @@ uint32_t HAL_GetTick(void)
*/
static int stm32f1_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -26,7 +26,7 @@
/**
* @brief map pin function to MODE register value
*/
static uint32_t __func_to_mode(int func)
static u32_t __func_to_mode(int func)
{
switch (func) {
case STM32F10X_PIN_CONFIG_ANALOG:
@ -46,7 +46,7 @@ static uint32_t __func_to_mode(int func)
/**
* @brief map pin function to CNF register value
*/
static uint32_t __func_to_cnf(int func)
static u32_t __func_to_cnf(int func)
{
switch (func) {
case STM32F10X_PIN_CONFIG_ANALOG:
@ -97,7 +97,7 @@ int stm32_gpio_flags_to_conf(int flags, int *pincfg)
return 0;
}
int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
{
volatile struct stm32f10x_gpio *gpio =
(struct stm32f10x_gpio *)(base_addr);
@ -107,7 +107,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
/* pins are configured in CRL (0-7) and CRH (8-15)
* registers
*/
volatile uint32_t *reg = &gpio->crl;
volatile u32_t *reg = &gpio->crl;
ARG_UNUSED(altf);
@ -144,7 +144,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
return 0;
}
int stm32_gpio_set(uint32_t *base, int pin, int value)
int stm32_gpio_set(u32_t *base, int pin, int value)
{
struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;
@ -159,7 +159,7 @@ int stm32_gpio_set(uint32_t *base, int pin, int value)
return 0;
}
int stm32_gpio_get(uint32_t *base, int pin)
int stm32_gpio_get(u32_t *base, int pin)
{
struct stm32f10x_gpio *gpio = (struct stm32f10x_gpio *)base;

View file

@ -29,27 +29,27 @@ enum {
/* 3.3.3 FLASH_ACR */
union ef_acr {
uint32_t val;
u32_t val;
struct {
uint32_t latency :3 __packed;
uint32_t hlfcya :1 __packed;
uint32_t prftbe :1 __packed;
uint32_t prftbs :1 __packed;
uint32_t rsvd__6_31 :26 __packed;
u32_t latency :3 __packed;
u32_t hlfcya :1 __packed;
u32_t prftbe :1 __packed;
u32_t prftbs :1 __packed;
u32_t rsvd__6_31 :26 __packed;
} bit;
};
/* 3.3.3 Embedded flash registers */
struct stm32_flash {
union ef_acr acr;
uint32_t keyr;
uint32_t optkeyr;
uint32_t sr;
uint32_t cr;
uint32_t ar;
uint32_t rsvd;
uint32_t obr;
uint32_t wrpr;
u32_t keyr;
u32_t optkeyr;
u32_t sr;
u32_t cr;
u32_t ar;
u32_t rsvd;
u32_t obr;
u32_t wrpr;
};
/* list of device commands */

View file

@ -18,60 +18,60 @@
*/
struct stm32f3x_gpio {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t idr;
uint32_t odr;
uint32_t bsrr;
uint32_t lckr;
uint32_t afrl;
uint32_t afrh;
uint32_t brr;
u32_t moder;
u32_t otyper;
u32_t ospeedr;
u32_t pupdr;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t lckr;
u32_t afrl;
u32_t afrh;
u32_t brr;
};
union syscfg_cfgr1 {
uint32_t val;
u32_t val;
struct {
uint32_t mem_mode :2 __packed;
uint32_t rsvd__2_5 :4 __packed;
uint32_t tim1_itr3_rmo :1 __packed;
uint32_t dac_trig_rmp :1 __packed;
uint32_t rsvd__8_10 :3 __packed;
uint32_t tim16_dma_rmp :1 __packed;
uint32_t tim17_dma_rmp :1 __packed;
uint32_t tim16_dac1_dma_rmp :1 __packed;
uint32_t tim17_dac2_dma_rmp :1 __packed;
uint32_t dac2_ch1_dma_rmp :1 __packed;
uint32_t i2c_pb6_fmp :1 __packed;
uint32_t i2c_pb7_fmp :1 __packed;
uint32_t i2c_pb8_fmp :1 __packed;
uint32_t i2c_pb9_fmp :1 __packed;
uint32_t i2c1_fmp :1 __packed;
uint32_t rsvd__21 :1 __packed;
uint32_t encoder_mode :2 __packed;
uint32_t rsvd__24_25 :2 __packed;
uint32_t fpu_ie :6 __packed;
u32_t mem_mode :2 __packed;
u32_t rsvd__2_5 :4 __packed;
u32_t tim1_itr3_rmo :1 __packed;
u32_t dac_trig_rmp :1 __packed;
u32_t rsvd__8_10 :3 __packed;
u32_t tim16_dma_rmp :1 __packed;
u32_t tim17_dma_rmp :1 __packed;
u32_t tim16_dac1_dma_rmp :1 __packed;
u32_t tim17_dac2_dma_rmp :1 __packed;
u32_t dac2_ch1_dma_rmp :1 __packed;
u32_t i2c_pb6_fmp :1 __packed;
u32_t i2c_pb7_fmp :1 __packed;
u32_t i2c_pb8_fmp :1 __packed;
u32_t i2c_pb9_fmp :1 __packed;
u32_t i2c1_fmp :1 __packed;
u32_t rsvd__21 :1 __packed;
u32_t encoder_mode :2 __packed;
u32_t rsvd__24_25 :2 __packed;
u32_t fpu_ie :6 __packed;
} bit;
};
union syscfg_rcr {
uint32_t val;
u32_t val;
struct {
uint32_t page0_wp :1 __packed;
uint32_t page1_wp :1 __packed;
uint32_t page2_wp :1 __packed;
uint32_t page3_wp :1 __packed;
uint32_t rsvd__4_31 :28 __packed;
u32_t page0_wp :1 __packed;
u32_t page1_wp :1 __packed;
u32_t page2_wp :1 __packed;
u32_t page3_wp :1 __packed;
u32_t rsvd__4_31 :28 __packed;
} bit;
};
union syscfg__exticr {
uint32_t val;
u32_t val;
struct {
uint16_t exti;
uint16_t rsvd__16_31;
u16_t exti;
u16_t rsvd__16_31;
} bit;
};
@ -82,21 +82,21 @@ struct stm32f3x_syscfg {
union syscfg__exticr exticr2;
union syscfg__exticr exticr3;
union syscfg__exticr exticr4;
uint32_t cfgr2;
uint32_t rsvd_0x1C;
uint32_t rsvd_0x20;
uint32_t rsvd_0x24;
uint32_t rsvd_0x28;
uint32_t rsvd_0x2C;
uint32_t rsvd_0x30;
uint32_t rsvd_0x34;
uint32_t rsvd_0x38;
uint32_t rsvd_0x3C;
uint32_t rsvd_0x40;
uint32_t rsvd_0x44;
uint32_t rsvd_0x48;
uint32_t rsvd_0x4C;
uint32_t cfgr3;
u32_t cfgr2;
u32_t rsvd_0x1C;
u32_t rsvd_0x20;
u32_t rsvd_0x24;
u32_t rsvd_0x28;
u32_t rsvd_0x2C;
u32_t rsvd_0x30;
u32_t rsvd_0x34;
u32_t rsvd_0x38;
u32_t rsvd_0x3C;
u32_t rsvd_0x40;
u32_t rsvd_0x44;
u32_t rsvd_0x48;
u32_t rsvd_0x4C;
u32_t cfgr3;
};
#endif /* _STM32F3X_GPIO_REGISTERS_H_ */

View file

@ -37,7 +37,7 @@ uint32_t HAL_GetTick(void)
*/
static int stm32f3_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -25,7 +25,7 @@
/**
* @brief map pin function to MODE register value
*/
static uint32_t func_to_mode(int func)
static u32_t func_to_mode(int func)
{
switch (func) {
case STM32F3X_PIN_CONFIG_ANALOG:
@ -95,7 +95,7 @@ int stm32_gpio_flags_to_conf(int flags, int *pincfg)
return 0;
}
int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
{
volatile struct stm32f3x_gpio *gpio =
(struct stm32f3x_gpio *)(base_addr);
@ -112,7 +112,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
if (cmode == STM32F3X_PIN_CONFIG_AF) {
/* alternate function setup */
int af = STM32_AF(conf);
volatile uint32_t *afr = &gpio->afrl;
volatile u32_t *afr = &gpio->afrl;
int crpin = pin;
if (crpin > 7) {
@ -156,7 +156,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
return 0;
}
int stm32_gpio_set(uint32_t *base, int pin, int value)
int stm32_gpio_set(u32_t *base, int pin, int value)
{
struct stm32f3x_gpio *gpio = (struct stm32f3x_gpio *)base;
@ -171,7 +171,7 @@ int stm32_gpio_set(uint32_t *base, int pin, int value)
return 0;
}
int stm32_gpio_get(uint32_t *base, int pin)
int stm32_gpio_get(u32_t *base, int pin)
{
struct stm32f3x_gpio *gpio = (struct stm32f3x_gpio *)base;

View file

@ -34,8 +34,8 @@ struct stm32f4x_flash_sector stm32f4xx_sectors[] = {
#endif
};
#define STM32F4X_FLASH_TIMEOUT ((uint32_t) 0x000B0000)
#define STM32F4X_SECTOR_MASK ((uint32_t) 0xFFFFFF07)
#define STM32F4X_FLASH_TIMEOUT ((u32_t) 0x000B0000)
#define STM32F4X_SECTOR_MASK ((u32_t) 0xFFFFFF07)
#define STM32F4X_SECTORS ARRAY_SIZE(stm32f4xx_sectors)
#define STM32F4X_FLASH_END \

View file

@ -25,27 +25,27 @@ enum {
};
union __flash_acr {
uint32_t val;
u32_t val;
struct {
uint32_t latency :4 __packed;
uint32_t rsvd__4_7 :4 __packed;
uint32_t prften :1 __packed;
uint32_t icen :1 __packed;
uint32_t dcen :1 __packed;
uint32_t icrst :1 __packed;
uint32_t dcrst :1 __packed;
uint32_t rsvd__13_31 :19 __packed;
u32_t latency :4 __packed;
u32_t rsvd__4_7 :4 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t rsvd__13_31 :19 __packed;
} bit;
};
/* 3.8.7 Embedded flash registers */
struct stm32f4x_flash {
volatile union __flash_acr acr;
volatile uint32_t key;
volatile uint32_t optkey;
volatile uint32_t status;
volatile uint32_t ctrl;
volatile uint32_t optctrl;
volatile u32_t key;
volatile u32_t optkey;
volatile u32_t status;
volatile u32_t ctrl;
volatile u32_t optctrl;
};
/**
@ -56,7 +56,7 @@ struct stm32f4x_flash {
static inline void __setup_flash(void)
{
volatile struct stm32f4x_flash *regs;
uint32_t tmpreg = 0;
u32_t tmpreg = 0;
regs = (struct stm32f4x_flash *) FLASH_R_BASE;

View file

@ -19,34 +19,34 @@
/* 8.4 GPIO registers - each GPIO port controls 16 pins */
struct stm32f4x_gpio {
uint32_t mode;
uint32_t otype;
uint32_t ospeed;
uint32_t pupdr;
uint32_t idr;
uint32_t odr;
uint32_t bsr;
uint32_t lck;
uint32_t afr[2];
u32_t mode;
u32_t otype;
u32_t ospeed;
u32_t pupdr;
u32_t idr;
u32_t odr;
u32_t bsr;
u32_t lck;
u32_t afr[2];
};
union syscfg_exticr {
uint32_t val;
u32_t val;
struct {
uint16_t rsvd__16_31;
uint16_t exti;
u16_t rsvd__16_31;
u16_t exti;
} bit;
};
/* 7.2 SYSCFG registers */
struct stm32f4x_syscfg {
uint32_t memrmp;
uint32_t pmc;
u32_t memrmp;
u32_t pmc;
union syscfg_exticr exticr1;
union syscfg_exticr exticr2;
union syscfg_exticr exticr3;
union syscfg_exticr exticr4;
uint32_t cmpcr;
u32_t cmpcr;
};
#endif /* _STM32F4X_GPIO_REGISTERS_H_ */

View file

@ -66,58 +66,58 @@ enum {
};
union __rcc_cr {
uint32_t val;
u32_t val;
struct {
uint32_t hsion :1 __packed;
uint32_t hsirdy :1 __packed;
uint32_t rsvd__2 :1 __packed;
uint32_t hsitrim :5 __packed;
uint32_t hsical :8 __packed;
uint32_t hseon :1 __packed;
uint32_t hserdy :1 __packed;
uint32_t hsebyp :1 __packed;
uint32_t csson :1 __packed;
uint32_t rsvd__20_23 :4 __packed;
uint32_t pllon :1 __packed;
uint32_t pllrdy :1 __packed;
uint32_t plli2son :1 __packed;
uint32_t plli2srdy :1 __packed;
uint32_t pllsaion :1 __packed;
uint32_t pllsairdy :1 __packed;
uint32_t rsvd__30_31 :2 __packed;
u32_t hsion :1 __packed;
u32_t hsirdy :1 __packed;
u32_t rsvd__2 :1 __packed;
u32_t hsitrim :5 __packed;
u32_t hsical :8 __packed;
u32_t hseon :1 __packed;
u32_t hserdy :1 __packed;
u32_t hsebyp :1 __packed;
u32_t csson :1 __packed;
u32_t rsvd__20_23 :4 __packed;
u32_t pllon :1 __packed;
u32_t pllrdy :1 __packed;
u32_t plli2son :1 __packed;
u32_t plli2srdy :1 __packed;
u32_t pllsaion :1 __packed;
u32_t pllsairdy :1 __packed;
u32_t rsvd__30_31 :2 __packed;
} bit;
};
union __rcc_pllcfgr {
uint32_t val;
u32_t val;
struct {
uint32_t pllm :6 __packed;
uint32_t plln :9 __packed;
uint32_t rsvd__15 :1 __packed;
uint32_t pllp :2 __packed;
uint32_t rsvd__18_21 :4 __packed;
uint32_t pllsrc :1 __packed;
uint32_t rsvd__23 :1 __packed;
uint32_t pllq :4 __packed;
uint32_t rsvd__28_31 :4 __packed;
u32_t pllm :6 __packed;
u32_t plln :9 __packed;
u32_t rsvd__15 :1 __packed;
u32_t pllp :2 __packed;
u32_t rsvd__18_21 :4 __packed;
u32_t pllsrc :1 __packed;
u32_t rsvd__23 :1 __packed;
u32_t pllq :4 __packed;
u32_t rsvd__28_31 :4 __packed;
} bit;
};
union __rcc_cfgr {
uint32_t val;
u32_t val;
struct {
uint32_t sw :2 __packed;
uint32_t sws :2 __packed;
uint32_t hpre :4 __packed;
uint32_t rsvd__8_9 :2 __packed;
uint32_t ppre1 :3 __packed;
uint32_t ppre2 :3 __packed;
uint32_t rtcpre :5 __packed;
uint32_t mco1 :2 __packed;
uint32_t i2sscr :1 __packed;
uint32_t mco1pre :3 __packed;
uint32_t mco2pre :3 __packed;
uint32_t mco2 :2 __packed;
u32_t sw :2 __packed;
u32_t sws :2 __packed;
u32_t hpre :4 __packed;
u32_t rsvd__8_9 :2 __packed;
u32_t ppre1 :3 __packed;
u32_t ppre2 :3 __packed;
u32_t rtcpre :5 __packed;
u32_t mco1 :2 __packed;
u32_t i2sscr :1 __packed;
u32_t mco1pre :3 __packed;
u32_t mco2pre :3 __packed;
u32_t mco2 :2 __packed;
} bit;
};
@ -125,35 +125,35 @@ struct stm32f4x_rcc {
union __rcc_cr cr;
union __rcc_pllcfgr pllcfgr;
union __rcc_cfgr cfgr;
uint32_t cir;
uint32_t ahb1rstr;
uint32_t ahb2rstr;
uint32_t ahb3rstr;
uint32_t rsvd0;
uint32_t apb1rstr;
uint32_t apb2rstr;
uint32_t rsvd1[2];
uint32_t ahb1enr;
uint32_t ahb2enr;
uint32_t ahb3enr;
uint32_t rsvd2;
uint32_t apb1enr;
uint32_t apb2enr;
uint32_t rsvd3[2];
uint32_t ahb1lpenr;
uint32_t ahb2lpenr;
uint32_t ahb3lpenr;
uint32_t rsvd4;
uint32_t apb1lpenr;
uint32_t apb2lpenr;
uint32_t rsvd5[2];
uint32_t bdcr;
uint32_t csr;
uint32_t rsvd6[2];
uint32_t sscgr;
uint32_t plli2scfgr;
uint32_t rsvd7;
uint32_t dckcfgr;
u32_t cir;
u32_t ahb1rstr;
u32_t ahb2rstr;
u32_t ahb3rstr;
u32_t rsvd0;
u32_t apb1rstr;
u32_t apb2rstr;
u32_t rsvd1[2];
u32_t ahb1enr;
u32_t ahb2enr;
u32_t ahb3enr;
u32_t rsvd2;
u32_t apb1enr;
u32_t apb2enr;
u32_t rsvd3[2];
u32_t ahb1lpenr;
u32_t ahb2lpenr;
u32_t ahb3lpenr;
u32_t rsvd4;
u32_t apb1lpenr;
u32_t apb2lpenr;
u32_t rsvd5[2];
u32_t bdcr;
u32_t csr;
u32_t rsvd6[2];
u32_t sscgr;
u32_t plli2scfgr;
u32_t rsvd7;
u32_t dckcfgr;
};
#endif /* _STM32F4X_CLOCK_H_ */

View file

@ -38,7 +38,7 @@ uint32_t HAL_GetTick(void)
*/
static int st_stm32f4_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -25,7 +25,7 @@
/**
* @brief map pin function to MODE register value
*/
static uint32_t __func_to_mode(int func)
static u32_t __func_to_mode(int func)
{
switch (func) {
case STM32F4X_PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
@ -56,7 +56,7 @@ static uint32_t __func_to_mode(int func)
/**
* @brief map pin function to OTYPE register value
*/
static uint32_t __func_to_otype(int func)
static u32_t __func_to_otype(int func)
{
switch (func) {
case STM32F4X_PIN_CONFIG_DRIVE_OPEN_DRAIN:
@ -74,7 +74,7 @@ static uint32_t __func_to_otype(int func)
/**
* @brief map pin function to OSPEED register value
*/
static uint32_t __func_to_ospeed(int func)
static u32_t __func_to_ospeed(int func)
{
switch (func) {
case STM32F4X_PIN_CONFIG_DRIVE_PUSH_PULL:
@ -99,7 +99,7 @@ static uint32_t __func_to_ospeed(int func)
/**
* @brief map pin function to PUPD register value
*/
static uint32_t __func_to_pupd(int func)
static u32_t __func_to_pupd(int func)
{
switch (func) {
case STM32F4X_PIN_CONFIG_DRIVE_PUSH_PULL:
@ -159,15 +159,15 @@ int stm32_gpio_flags_to_conf(int flags, int *pincfg)
return 0;
}
int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
int stm32_gpio_configure(u32_t *base_addr, int pin, int conf, int altf)
{
volatile struct stm32f4x_gpio *gpio =
(struct stm32f4x_gpio *)(base_addr);
uint32_t mode = __func_to_mode(conf);
uint32_t otype = __func_to_otype(conf);
uint32_t ospeed = __func_to_ospeed(conf);
uint32_t pupd = __func_to_pupd(conf);
uint32_t tmpreg = 0;
u32_t mode = __func_to_mode(conf);
u32_t otype = __func_to_otype(conf);
u32_t ospeed = __func_to_ospeed(conf);
u32_t pupd = __func_to_pupd(conf);
u32_t tmpreg = 0;
/* TODO: validate if indeed alternate */
if (altf) {
@ -206,7 +206,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int conf, int altf)
return 0;
}
int stm32_gpio_set(uint32_t *base, int pin, int value)
int stm32_gpio_set(u32_t *base, int pin, int value)
{
struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;
@ -221,7 +221,7 @@ int stm32_gpio_set(uint32_t *base, int pin, int value)
return 0;
}
int stm32_gpio_get(uint32_t *base, int pin)
int stm32_gpio_get(u32_t *base, int pin)
{
struct stm32f4x_gpio *gpio = (struct stm32f4x_gpio *)base;

View file

@ -18,46 +18,46 @@ enum {
/* 3.7.1 FLASH_ACR */
union __ef_acr {
uint32_t val;
u32_t val;
struct {
uint32_t latency :3 __packed;
uint32_t rsvd__3_7 :5 __packed;
uint32_t prften :1 __packed;
uint32_t icen :1 __packed;
uint32_t dcen :1 __packed;
uint32_t icrst :1 __packed;
uint32_t dcrst :1 __packed;
uint32_t run_pd :1 __packed;
uint32_t sleep_pd :1 __packed;
uint32_t rsvd__16_31 :17 __packed;
u32_t latency :3 __packed;
u32_t rsvd__3_7 :5 __packed;
u32_t prften :1 __packed;
u32_t icen :1 __packed;
u32_t dcen :1 __packed;
u32_t icrst :1 __packed;
u32_t dcrst :1 __packed;
u32_t run_pd :1 __packed;
u32_t sleep_pd :1 __packed;
u32_t rsvd__16_31 :17 __packed;
} bit;
};
/* FLASH register map */
struct stm32l4x_flash {
union __ef_acr acr;
uint32_t pdkeyr;
uint32_t keyr;
uint32_t optkeyr;
uint32_t sr;
uint32_t cr;
uint32_t eccr;
uint32_t rsvd_0;
uint32_t optr;
uint32_t pcrop1sr;
uint32_t pcrop1er;
uint32_t wrp1ar;
uint32_t wrp1br;
uint32_t rsvd_2[4];
u32_t pdkeyr;
u32_t keyr;
u32_t optkeyr;
u32_t sr;
u32_t cr;
u32_t eccr;
u32_t rsvd_0;
u32_t optr;
u32_t pcrop1sr;
u32_t pcrop1er;
u32_t wrp1ar;
u32_t wrp1br;
u32_t rsvd_2[4];
/*
* The registers below are only present on STM32L4x2, STM32L4x5,
* STM32L4x6.
*/
uint32_t pcrop2sr;
uint32_t pcrop2er;
uint32_t wrp2ar;
uint32_t wrp2br;
u32_t pcrop2sr;
u32_t pcrop2er;
u32_t wrp2ar;
u32_t wrp2br;
};
#endif /* _STM32L4X_FLASH_REGISTERS_H_ */

View file

@ -38,7 +38,7 @@ uint32_t HAL_GetTick(void)
*/
static int stm32l4_init(struct device *arg)
{
uint32_t key;
u32_t key;
ARG_UNUSED(arg);

View file

@ -57,23 +57,23 @@ enum {
/* GPIO registers - each GPIO port controls 16 pins */
struct stm32l4x_gpio {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t idr;
uint32_t odr;
uint32_t bsrr;
uint32_t lckr;
uint32_t afr[2];
uint32_t brr;
uint32_t ascr; /* Only present on STM32L4x1, STM32L4x5, STM32L4x6 */
u32_t moder;
u32_t otyper;
u32_t ospeedr;
u32_t pupdr;
u32_t idr;
u32_t odr;
u32_t bsrr;
u32_t lckr;
u32_t afr[2];
u32_t brr;
u32_t ascr; /* Only present on STM32L4x1, STM32L4x5, STM32L4x6 */
};
/**
* @brief map pin function to MODE register value
*/
static uint32_t func_to_mode(int conf, unsigned int afnum)
static u32_t func_to_mode(int conf, unsigned int afnum)
{
/* If an alternate function is specified */
if (afnum) {
@ -94,7 +94,7 @@ static uint32_t func_to_mode(int conf, unsigned int afnum)
return STM32L4X_MODER_INPUT_MODE;
}
static uint32_t func_to_otype(int conf)
static u32_t func_to_otype(int conf)
{
switch (conf) {
case STM32L4X_PIN_CONFIG_OPEN_DRAIN:
@ -108,7 +108,7 @@ static uint32_t func_to_otype(int conf)
return STM32L4X_OTYPER_PUSH_PULL;
}
static uint32_t func_to_pupd(int conf)
static u32_t func_to_pupd(int conf)
{
switch (conf) {
case STM32L4X_PIN_CONFIG_ANALOG:
@ -158,7 +158,7 @@ int stm32_gpio_flags_to_conf(int flags, int *pincfg)
return 0;
}
int stm32_gpio_configure(uint32_t *base_addr, int pin, int pinconf, int afnum)
int stm32_gpio_configure(u32_t *base_addr, int pin, int pinconf, int afnum)
{
volatile struct stm32l4x_gpio *gpio =
(struct stm32l4x_gpio *)(base_addr);
@ -166,7 +166,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int pinconf, int afnum)
unsigned int pin_shift = pin << 1;
unsigned int afr_bank = pin / 8;
unsigned int afr_shift = (pin % 8) << 2;
uint32_t scratch;
u32_t scratch;
mode = func_to_mode(pinconf, afnum);
otype = func_to_otype(pinconf);
@ -187,7 +187,7 @@ int stm32_gpio_configure(uint32_t *base_addr, int pin, int pinconf, int afnum)
return 0;
}
int stm32_gpio_set(uint32_t *base, int pin, int value)
int stm32_gpio_set(u32_t *base, int pin, int value)
{
struct stm32l4x_gpio *gpio = (struct stm32l4x_gpio *)base;
int pval = 1 << (pin & 0xf);
@ -201,7 +201,7 @@ int stm32_gpio_set(uint32_t *base, int pin, int value)
return 0;
}
int stm32_gpio_get(uint32_t *base, int pin)
int stm32_gpio_get(u32_t *base, int pin)
{
struct stm32l4x_gpio *gpio = (struct stm32l4x_gpio *)base;
@ -212,7 +212,7 @@ int stm32_gpio_enable_int(int port, int pin)
{
struct stm32l4x_syscfg *syscfg = (struct stm32l4x_syscfg *)SYSCFG_BASE;
struct device *clk = device_get_binding(STM32_CLOCK_CONTROL_NAME);
uint32_t *reg;
u32_t *reg;
/* Enable SYSCFG clock */
struct stm32_pclken pclken = {

View file

@ -11,16 +11,16 @@
/* SYSCFG registers */
struct stm32l4x_syscfg {
uint32_t memrmp;
uint32_t cfgr1;
uint32_t exticr1;
uint32_t exticr2;
uint32_t exticr3;
uint32_t exticr4;
uint32_t scsr;
uint32_t cfgr2;
uint32_t swpr;
uint32_t skr;
u32_t memrmp;
u32_t cfgr1;
u32_t exticr1;
u32_t exticr2;
u32_t exticr3;
u32_t exticr4;
u32_t scsr;
u32_t cfgr2;
u32_t swpr;
u32_t skr;
};
#endif /* _STM32L4X_SYSCFG_REGISTERS_H_ */

View file

@ -57,99 +57,99 @@ extern "C" {
#define _SCP_CRYSTAL_8_192MHZ 15
union __rcc {
uint32_t value;
u32_t value;
struct {
uint32_t moscdis : 1 __packed;
uint32_t ioscdis : 1 __packed;
uint32_t rsvd__2_3 : 2 __packed;
uint32_t oscsrc : 2 __packed;
uint32_t xtal : 4 __packed;
uint32_t rsvd__10 : 1 __packed;
uint32_t bypass : 1 __packed;
uint32_t rsvd__12 : 1 __packed;
uint32_t pwrdn : 1 __packed;
uint32_t rsvd__14_16 : 3 __packed;
uint32_t pwmdiv : 3 __packed; /* 2**(n+1) */
uint32_t usepwmdiv : 1 __packed;
uint32_t rsvd__21 : 1 __packed;
uint32_t usesysdiv : 1 __packed;
uint32_t sysdiv : 4 __packed;
uint32_t acg : 1 __packed;
uint32_t rsvd__28_31 : 4 __packed;
u32_t moscdis : 1 __packed;
u32_t ioscdis : 1 __packed;
u32_t rsvd__2_3 : 2 __packed;
u32_t oscsrc : 2 __packed;
u32_t xtal : 4 __packed;
u32_t rsvd__10 : 1 __packed;
u32_t bypass : 1 __packed;
u32_t rsvd__12 : 1 __packed;
u32_t pwrdn : 1 __packed;
u32_t rsvd__14_16 : 3 __packed;
u32_t pwmdiv : 3 __packed; /* 2**(n+1) */
u32_t usepwmdiv : 1 __packed;
u32_t rsvd__21 : 1 __packed;
u32_t usesysdiv : 1 __packed;
u32_t sysdiv : 4 __packed;
u32_t acg : 1 __packed;
u32_t rsvd__28_31 : 4 __packed;
} bit;
};
union __rcc2 {
uint32_t value;
u32_t value;
struct {
uint8_t rsvd__0_3 : 4 __packed;
uint8_t oscsrc2 : 3 __packed;
uint16_t rsvd__7_10 : 4 __packed;
uint8_t bypass2 : 1 __packed;
uint8_t rsvd__12 : 1 __packed;
uint8_t pwrdn2 : 1 __packed;
uint16_t rsvd__14_22 : 9 __packed;
uint16_t sysdiv2 : 6 __packed;
uint8_t rsvd__29_30 : 2 __packed;
uint8_t usercc2 : 1 __packed;
u8_t rsvd__0_3 : 4 __packed;
u8_t oscsrc2 : 3 __packed;
u16_t rsvd__7_10 : 4 __packed;
u8_t bypass2 : 1 __packed;
u8_t rsvd__12 : 1 __packed;
u8_t pwrdn2 : 1 __packed;
u16_t rsvd__14_22 : 9 __packed;
u16_t sysdiv2 : 6 __packed;
u8_t rsvd__29_30 : 2 __packed;
u8_t usercc2 : 1 __packed;
} bit;
};
struct __scp {
uint32_t did0; /* 0x000 RO Device ID*/
uint32_t did1; /* 0x004 RO Device ID*/
uint32_t dc0; /* 0x008 RO Device Capabilities */
uint32_t dc1; /* 0x00c RO Device Capabilities */
uint32_t dc2; /* 0x010 RO Device Capabilities */
uint32_t dc3; /* 0x014 RO Device Capabilities */
uint32_t dc4; /* 0x018 RO Device capabilities */
u32_t did0; /* 0x000 RO Device ID*/
u32_t did1; /* 0x004 RO Device ID*/
u32_t dc0; /* 0x008 RO Device Capabilities */
u32_t dc1; /* 0x00c RO Device Capabilities */
u32_t dc2; /* 0x010 RO Device Capabilities */
u32_t dc3; /* 0x014 RO Device Capabilities */
u32_t dc4; /* 0x018 RO Device capabilities */
uint32_t rsvd__01c_02f[(0x30 - 0x1c) / 4];
u32_t rsvd__01c_02f[(0x30 - 0x1c) / 4];
uint32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */
uint32_t ldopctl; /* 0x034 RW LDO Power ConTroL */
u32_t pborctl; /* 0x030 RW Brown-Out Reset ConTroL */
u32_t ldopctl; /* 0x034 RW LDO Power ConTroL */
uint32_t rsvd__038_03f[(0x40 - 0x38) / 4];
u32_t rsvd__038_03f[(0x40 - 0x38) / 4];
uint32_t srcr0; /* 0x040 RW Software Reset Control Register */
uint32_t srcr1; /* 0x044 RW Software Reset Control Register */
uint32_t srcr2; /* 0x048 RW Software Reset Control Register */
u32_t srcr0; /* 0x040 RW Software Reset Control Register */
u32_t srcr1; /* 0x044 RW Software Reset Control Register */
u32_t srcr2; /* 0x048 RW Software Reset Control Register */
uint32_t rsvd__04c_04f;
u32_t rsvd__04c_04f;
uint32_t ris; /* 0x050 RO Raw Interrupt Status */
uint32_t imc; /* 0x054 RW Interrupt Mask Control */
uint32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */
uint32_t resc; /* 0x05C RW RESet Cause */
u32_t ris; /* 0x050 RO Raw Interrupt Status */
u32_t imc; /* 0x054 RW Interrupt Mask Control */
u32_t misc; /* 0x058 RW1C Masked Int. Status & Clear */
u32_t resc; /* 0x05C RW RESet Cause */
struct {
union __rcc rcc; /* 0x060 RW Run-mode Clock Configuration */
uint32_t pllcfg; /* 0x064 RW xtal-to-pll translation */
u32_t pllcfg; /* 0x064 RW xtal-to-pll translation */
uint32_t rsvd__068_06f[(0x70 - 0x068) / 4];
u32_t rsvd__068_06f[(0x70 - 0x068) / 4];
union __rcc2 rcc2; /* 0x070 RW Run-mode Clock Configuration */
uint32_t rsvd__074_0ff[(0x100 - 0x074) / 4];
u32_t rsvd__074_0ff[(0x100 - 0x074) / 4];
uint32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */
uint32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */
uint32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */
u32_t rcgc0; /* 0x100 RW Run-mode Clock Gating */
u32_t rcgc1; /* 0x104 RW Run-mode Clock Gating */
u32_t rcgc2; /* 0x108 RW Run-mode Clock Gating */
uint32_t rsvd__10c_10f;
u32_t rsvd__10c_10f;
uint32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */
uint32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */
uint32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */
u32_t scgc0; /* 0x110 RW Sleep-mode Clock Gating */
u32_t scgc1; /* 0x114 RW Sleep-mode Clock Gating */
u32_t scgc2; /* 0x118 RW Sleep-mode Clock Gating */
uint32_t rsvd__11c_11f;
u32_t rsvd__11c_11f;
uint32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */
uint32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */
uint32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */
u32_t dcgc0; /* 0x120 RW Deep sleep mode Clock Gating */
u32_t dcgc1; /* 0x124 RW Deep sleep mode Clock Gating */
u32_t dcgc2; /* 0x128 RW Deep sleep mode Clock Gating */
uint32_t rsvd__12c_143[(0x144 - 0x12c) / 4];
u32_t rsvd__12c_143[(0x144 - 0x12c) / 4];
uint32_t
u32_t
dslpclkcfg; /* 0x144 RW Deep SLeeP CLocK ConFiGuration
*/
} clock;

View file

@ -18,7 +18,7 @@
#ifdef CONFIG_UART_STELLARIS
#include <uart.h>
#define RCGC1 (*((volatile uint32_t *)0x400FE104))
#define RCGC1 (*((volatile u32_t *)0x400FE104))
#define RCGC1_UART0_EN 0x00000001
#define RCGC1_UART1_EN 0x00000002