soc: esp32c2: ESP WiFi heap
Provide symbols for the creation of dynamic memory pool. Update the ROM-code SRAM usage according the IDF main. Fix static allocations size check. Increase iram_seg memory size for MCUboot. Signed-off-by: Marek Matej <marek.matej@espressif.com>
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2 changed files with 30 additions and 22 deletions
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@ -85,6 +85,9 @@ _rom_store_table = 0;
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_iram_dram_offset = IRAM_DRAM_OFFSET;
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/* Used as a pointer to the heap end */
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_heap_sentry = DRAM_RESERVED_START;
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SECTIONS
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{
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#ifdef CONFIG_BOOTLOADER_MCUBOOT
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@ -585,7 +588,7 @@ SECTIONS
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_image_ram_start = _iram_start - IRAM_DRAM_OFFSET;
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#include <zephyr/linker/ram-end.ld>
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ASSERT(((__bss_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "DRAM segment data does not fit.")
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ASSERT(((_end - ORIGIN(dram0_0_seg)) <= LENGTH(dram0_0_seg)), "SRAM code/data does not fit.")
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/* --- END OF DRAM --- */
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@ -7,9 +7,12 @@
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/* SRAM0 (16kB) memory */
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#define SRAM0_IRAM_START 0x4037c000
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#define SRAM0_SIZE 0x4000
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/* SRAM1 (256kB) memory */
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#define SRAM1_DRAM_START 0x3fca0000
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#define SRAM1_IRAM_START 0x40380000
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#define SRAM1_SIZE 0x40000
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/* ICache size is fixed to 16KB on ESP32-C2 */
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#define ICACHE_SIZE SRAM0_SIZE
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@ -17,42 +20,44 @@
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* Make sure the bootloader can load into main memory without overwriting itself.
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*
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* ESP32-C2 ROM static data usage is as follows:
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* - 0x3fccae00 - 0x3fcdc710: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdc710 - 0x3fcde710: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcde710 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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* - 0x3fccb264 - 0x3fcdcb70: Shared buffers, used in UART/USB/SPI download mode only
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* - 0x3fcdcb70 - 0x3fcdeb70: PRO CPU stack, can be reclaimed as heap after RTOS startup
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* - 0x3fcdeb70 - 0x3fce0000: ROM .bss and .data (not easily reclaimable)
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*
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* The 2nd stage bootloader can take space up to the end of ROM shared
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* buffers area (0x3fcdc710).
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* buffers area (0x3fcdcb70).
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*/
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/* The offset between Dbus and Ibus.
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* Used to convert between 0x403xxxxx and 0x3fcxxxxx addresses.
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*/
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#define IRAM_DRAM_OFFSET SRAM1_IRAM_START - SRAM1_DRAM_START
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#define DRAM_BUFFERS_START 0x3fccae00
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#define DRAM_STACK_START 0x3fcdc710
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#define DRAM_ROM_BSS_DATA_START 0x3fcde710
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#define IRAM_DRAM_OFFSET 0x6e0000
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/* Base address used for calculating memory layout
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* counted from Dbus backwards and back to the Ibus
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*/
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#define BOOTLOADER_USER_DRAM_END DRAM_BUFFERS_START
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#define DRAM_BUFFERS_START 0x3fccb264
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#define DRAM_STACK_START 0x3fcdcb70
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#define DRAM_ROM_BSS_DATA_START 0x3fcdeb70
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#define DRAM_RESERVED_START DRAM_STACK_START
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/* For safety margin between bootloader data section and startup stacks */
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#define BOOTLOADER_STACK_OVERHEAD 0x0
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/* These lengths can be adjusted, if necessary: */
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#define BOOTLOADER_DRAM_SEG_LEN 0x9800
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#define BOOTLOADER_IRAM_SEG_LEN 0x9800
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#define BOOTLOADER_DRAM_SEG_LEN 0xb000
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#define BOOTLOADER_IRAM_SEG_LEN 0xc800
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#define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400
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/* Base address used for calculating memory layout
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* counted from Dbus backwards and back to the Ibus
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*/
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#define BOOTLOADER_USER_DRAM_END (DRAM_BUFFERS_START + BOOTLOADER_STACK_OVERHEAD)
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/* Start of the lower region is determined by region size and the end of the higher region */
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#define BOOTLOADER_IRAM_LOADER_SEG_END (BOOTLOADER_USER_DRAM_END + \
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BOOTLOADER_STACK_OVERHEAD + IRAM_DRAM_OFFSET)
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#define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_END - \
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BOOTLOADER_IRAM_LOADER_SEG_LEN)
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#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
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#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - IRAM_DRAM_OFFSET - \
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BOOTLOADER_DRAM_SEG_LEN)
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#define BOOTLOADER_IRAM_LOADER_SEG_START \
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(BOOTLOADER_USER_DRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN + IRAM_DRAM_OFFSET)
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#define BOOTLOADER_IRAM_SEG_START \
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(BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
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#define BOOTLOADER_DRAM_SEG_START \
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(BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN - IRAM_DRAM_OFFSET)
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/* Flash */
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#ifdef CONFIG_FLASH_SIZE
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