ITE: drivers/flash: remove flash write protection API
This API has be removed in Zephyr 2.8, and does not need to be used as a static function. Because flash_it8xxx2_write_protection(false) is not supported. If the IT83XX_GCTRL_EPLR register in the flash_it8xxx2_write_protection(false) is written as 1, the flash write region will not be protected later, only be cleared by power-on reset. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
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1 changed files with 0 additions and 57 deletions
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@ -78,15 +78,6 @@ struct flash_it8xxx2_dev_data {
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/* Set FSCE# as low level by writing data to address xfff_fd00h */
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#define FLASH_FSCE_LOW_ADDRESS 0x0FFFFD00
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#define FWP_REG(bank) (bank / 8)
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#define FWP_MASK(bank) (1 << (bank % 8))
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enum flash_wp_interface {
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FLASH_WP_HOST = 0x01,
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FLASH_WP_DBGR = 0x02,
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FLASH_WP_EC = 0x04,
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};
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enum flash_status_mask {
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FLASH_SR_NO_BUSY = 0,
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/* Internal write operation is in progress */
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@ -353,30 +344,6 @@ void __ram_code ramcode_flash_erase(int addr, int cmd)
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ramcode_flash_cmd_write_disable();
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}
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/**
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* Protect flash banks until reboot.
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*
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* @param start_bank Start bank to protect
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* @param bank_count Number of banks to protect
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*/
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static void flash_protect_banks(int start_bank, int bank_count,
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enum flash_wp_interface wp_if)
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{
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int bank;
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for (bank = start_bank; bank < start_bank + bank_count; bank++) {
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if (wp_if & FLASH_WP_EC) {
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IT83XX_GCTRL_EWPR0PFEC(FWP_REG(bank)) |= FWP_MASK(bank);
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}
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if (wp_if & FLASH_WP_HOST) {
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IT83XX_GCTRL_EWPR0PFH(FWP_REG(bank)) |= FWP_MASK(bank);
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}
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if (wp_if & FLASH_WP_DBGR) {
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IT83XX_GCTRL_EWPR0PFD(FWP_REG(bank)) |= FWP_MASK(bank);
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}
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}
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}
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/* Read data from flash */
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static int __ram_code flash_it8xxx2_read(const struct device *dev, off_t offset,
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void *data, size_t len)
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@ -403,22 +370,6 @@ static int __ram_code flash_it8xxx2_read(const struct device *dev, off_t offset,
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return 0;
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}
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/* Enable or disable the write protection */
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static void flash_it8xxx2_write_protection(bool enable)
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{
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if (enable) {
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/* Protect the entire flash */
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flash_protect_banks(0, CHIP_FLASH_SIZE_BYTES /
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CHIP_FLASH_BANK_SIZE, FLASH_WP_EC);
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}
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/*
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* bit[0], eflash protect lock register which can only be write 1 and
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* only be cleared by power-on reset.
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*/
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IT83XX_GCTRL_EPLR |= IT83XX_GCTRL_EPLR_ENABLE;
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}
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/* Write data to the flash, page by page */
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static int __ram_code flash_it8xxx2_write(const struct device *dev, off_t offset,
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const void *src_data, size_t len)
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@ -449,16 +400,12 @@ static int __ram_code flash_it8xxx2_write(const struct device *dev, off_t offset
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*/
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key = irq_lock();
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flash_it8xxx2_write_protection(false);
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ramcode_flash_write(offset, len, src_data);
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ramcode_reset_i_cache();
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/* Get the ILM address of a flash offset. */
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offset |= CHIP_MAPPED_STORAGE_BASE;
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ret = ramcode_flash_verify(offset, len, src_data);
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flash_it8xxx2_write_protection(true);
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irq_unlock(key);
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k_sem_give(&data->sem);
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@ -496,8 +443,6 @@ static int __ram_code flash_it8xxx2_erase(const struct device *dev,
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*/
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key = irq_lock();
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flash_it8xxx2_write_protection(false);
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/* Always use sector erase command */
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for (; len > 0; len -= FLASH_ERASE_BLK_SZ) {
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ramcode_flash_erase(offset, FLASH_CMD_SECTOR_ERASE);
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@ -508,8 +453,6 @@ static int __ram_code flash_it8xxx2_erase(const struct device *dev,
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v_addr |= CHIP_MAPPED_STORAGE_BASE;
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ret = ramcode_flash_verify(v_addr, v_size, NULL);
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flash_it8xxx2_write_protection(true);
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irq_unlock(key);
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k_sem_give(&data->sem);
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