socs quark: Simplify IRQ configuration
IRQ numbers differ between x86 and ARC, as well as the bits that need to be touched in the interrupt routing masks. QMSI abstracts some of it and for the rest we do have the information needed. Add a macro to select the right IRQ number based on which core we are building for. Change-Id: I3e6680d10a0a23c98777d2831efe6819fcb54162 Signed-off-by: Iván Briano <ivan.briano@intel.com>
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@ -48,6 +48,15 @@
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/* IRQs */
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/* The CPU-visible IRQ numbers change between the ARC and IA cores,
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* and QMSI itself has no easy way to pick the correct one, though it
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* does have the necessary information to do it ourselves (in the meantime).
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* This macro will be used by the shim drivers to get the IRQ number to
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* use, and it should always be called using the QM_IRQ_*_INT macro
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* provided by QMSI.
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*/
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#define IRQ_GET_NUMBER(_irq) _irq##_VECTOR
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#define IRQ_TIMER0 16
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#define IRQ_TIMER1 17
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#define IRQ_I2C0_RX_AVAIL 18
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@ -39,6 +39,15 @@
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#define INT_UNMASK_IA (~0x00000001)
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/* The CPU-visible IRQ numbers change between the ARC and IA cores,
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* and QMSI itself has no easy way to pick the correct one, though it
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* does have the necessary information to do it ourselves (in the meantime).
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* This macro will be used by the shim drivers to get the IRQ number to
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* use, and it should always be called using the QM_IRQ_*_INT macro
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* provided by QMSI.
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*/
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#define IRQ_GET_NUMBER(_irq) _irq
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/*
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* PINMUX configuration settings
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*/
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@ -56,6 +56,15 @@
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#define ARC_RUN (ARC_HALT_INT_REDIR | ARC_RUN_REQ_A)
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#define ARC_HALT (ARC_HALT_INT_REDIR | ARC_HALT_REQ_A)
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/* The CPU-visible IRQ numbers change between the ARC and IA cores,
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* and QMSI itself has no easy way to pick the correct one, though it
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* does have the necessary information to do it ourselves (in the meantime).
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* This macro will be used by the shim drivers to get the IRQ number to
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* use, and it should always be called using the QM_IRQ_*_INT macro
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* provided by QMSI.
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*/
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#define IRQ_GET_NUMBER(_irq) _irq
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/*
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* PINMUX configuration settings
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*/
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