michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: Add support for the WCH CH32V303

Browse source 
Adds support for building an image for the ch32v303.

Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
This commit is contained in:
Miguel Gazquez 2025-02-11 14:17:06 +01:00 • committed by Benjamin Cabé
commit be9549be60
15 changed files with 444 additions and 1 deletions
Download patch file Download diff file Expand all files Collapse all files

2
drivers/timer/Kconfig.wch_ch32v00x
View file

@ -3,6 +3,6 @@
config CH32V00X_SYSTICK
bool "CH32V QingKe core systick timer"
depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C || SOC_SERIES_CH32V00X || SOC_SERIES_QINGKE_V4B
depends on SOC_SERIES_QINGKE_V2A || SOC_SERIES_QINGKE_V4C || SOC_SERIES_CH32V00X || SOC_SERIES_QINGKE_V4B || SOC_SERIES_QINGKE_V4F
default y
depends on DT_HAS_WCH_SYSTICK_ENABLED

8
dts/bindings/cpu/wch,qingke-v4f.yaml Normal file
View file

@ -0,0 +1,8 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
description: WCH QingKe V4F RISC-V MCU
compatible: "wch,qingke-v4f"
include: riscv,cpus.yaml

217
dts/riscv/wch/ch32v303/ch32v303.dtsi Normal file
View file

@ -0,0 +1,217 @@
/*
* Copyright (c) 2025 Bootlin
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <freq.h>
#include <mem.h>
#include <wch/qingke-v4f.dtsi>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
/ {
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "wch,ch32v00x-hse-clock";
clock-frequency = <DT_FREQ_M(32)>;
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "wch,ch32v00x-hsi-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "wch,ch32v20x_30x-pll-clock";
mul = <18>;
status = "disabled";
};
};
soc {
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(32)>;
};
flash: flash-controller@40022000 {
compatible = "wch,ch32v20x_30x-flash-controller";
reg = <0x40022000 0x400>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "soc-nv-flash";
reg = <0x08000000 DT_SIZE_K(480)>;
};
};
pwr: pwr@40007000 {
compatible = "wch,pwr";
reg = <0x40007000 16>;
};
pinctrl: pin-controller@40010000 {
compatible = "wch,20x_30x-afio";
reg = <0x40010000 16>;
#address-cells = <1>;
#size-cells = <1>;
clocks = <&rcc CH32V20X_V30X_CLOCK_AFIO>;
gpioa: gpio@40010800 {
compatible = "wch,gpio";
reg = <0x40010800 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
};
gpiob: gpio@40010C00 {
compatible = "wch,gpio";
reg = <0x40010C00 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
};
gpioc: gpio@40011000 {
compatible = "wch,gpio";
reg = <0x40011000 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
};
gpiod: gpio@40011400 {
compatible = "wch,gpio";
reg = <0x40011400 0x20>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <8>;
clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
};
};
usart1: uart@40013800 {
compatible = "wch,usart";
reg = <0x40013800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
interrupt-parent = <&pfic>;
interrupts = <53>;
status = "disabled";
};
usart2: uart@40004400 {
compatible = "wch,usart";
reg = <0x40004400 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
interrupt-parent = <&pfic>;
interrupts = <54>;
status = "disabled";
};
usart3: uart@40004800 {
compatible = "wch,usart";
reg = <0x40004800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
interrupt-parent = <&pfic>;
interrupts = <55>;
status = "disabled";
};
usart4: uart@40004c00 {
compatible = "wch,usart";
reg = <0x40004C00 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
interrupt-parent = <&pfic>;
interrupts = <68>;
status = "disabled";
};
usart5: uart@40005000 {
compatible = "wch,usart";
reg = <0x40005000 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART5>;
interrupt-parent = <&pfic>;
interrupts = <69>;
status = "disabled";
};
usart6: uart@40001800 {
compatible = "wch,usart";
reg = <0x40001800 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART6>;
interrupt-parent = <&pfic>;
interrupts = <87>;
status = "disabled";
};
usart7: uart@40001c00 {
compatible = "wch,usart";
reg = <0x40001c00 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART7>;
interrupt-parent = <&pfic>;
interrupts = <88>;
status = "disabled";
};
usart8: uart@40002000 {
compatible = "wch,usart";
reg = <0x40002000 0x20>;
clocks = <&rcc CH32V20X_V30X_CLOCK_USART8>;
interrupt-parent = <&pfic>;
interrupts = <89>;
status = "disabled";
};
rcc: rcc@40021000 {
compatible = "wch,rcc";
reg = <0x40021000 16>;
#clock-cells = <1>;
status = "okay";
};
dma1: dma@40020000 {
compatible = "wch,wch-dma";
reg = <0x40020000 0x90>;
clocks = <&rcc CH32V20X_V30X_CLOCK_DMA1>;
#dma-cells = <1>;
interrupt-parent = <&pfic>;
interrupts = <27>, <28>, <29>, <30>, <31>, <32>, <33>;
dma-channels = <7>;
};
dma2: dma@40020400 {
compatible = "wch,wch-dma";
reg = <0x40020400 0x90>;
clocks = <&rcc CH32V20X_V30X_CLOCK_DMA2>;
#dma-cells = <1>;
interrupt-parent = <&pfic>;
interrupts = <72>, <73>, <74>, <75>, <76>, <98>, <99>, <100>,
<101>, <102>, <103>;
dma-channels = <11>;
};
};
};
&cpu0 {
clock-frequency = <DT_FREQ_M(144)>;
};

46
dts/riscv/wch/qingke-v4f.dtsi Normal file
View file

@ -0,0 +1,46 @@
/*
* Copyright (c) 2025 Bootlin
*
* SPDX-License-Identifier: Apache-2.0
*/
/ {
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "wch,qingke-v4f";
reg = <0>;
riscv,isa = "rv32imacf_zicsr_zifencei";
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
pfic: interrupt-controller@e000e000 {
compatible = "wch,pfic";
#address-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
reg = <0xe000e000 0x10>;
status = "okay";
};
systick: systimer@e000f000 {
compatible = "wch,systick";
reg = <0xe000f000 0x10>;
status = "okay";
interrupt-parent = <&pfic>;
interrupts = <12>;
};
};
};

9
modules/hal_wch/hal_ch32fun.h
View file

@ -27,4 +27,13 @@
#include <ch32fun.h>
#endif
#if defined(CONFIG_SOC_SERIES_QINGKE_V4F)
#define CH32V30x 1
#if defined(CONFIG_SOC_CH32V303)
#define CH32V30x_D8 1
#endif
#include <ch32fun.h>
#endif
#endif

10
soc/wch/ch32v/qingke_v4f/CMakeLists.txt Normal file
View file

@ -0,0 +1,10 @@
# Copyright (c) 2024 Michael Hope
# Copyright (c) 2024 Jianxiong Gu
# SPDX-License-Identifier: Apache-2.0
zephyr_sources(
soc_irq.S
vector.S
)
zephyr_include_directories(.)

11
soc/wch/ch32v/qingke_v4f/Kconfig Normal file
View file

@ -0,0 +1,11 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_QINGKE_V4F
select RISCV_ISA_RV32I
select RISCV_ISA_EXT_M
select RISCV_ISA_EXT_A
select RISCV_ISA_EXT_C
select RISCV_ISA_EXT_F
select RISCV_ISA_EXT_ZICSR
select RISCV_ISA_EXT_ZIFENCEI

14
soc/wch/ch32v/qingke_v4f/Kconfig.defconfig Normal file
View file

@ -0,0 +1,14 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_QINGKE_V4F
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
config CLOCK_CONTROL
default y
rsource "Kconfig.defconfig.*"
endif # SOC_SERIES_QINGKE_V4F

12
soc/wch/ch32v/qingke_v4f/Kconfig.defconfig.ch32v303 Normal file
View file

@ -0,0 +1,12 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
if SOC_CH32V303
config VECTOR_TABLE_SIZE
default 103
config NUM_IRQS
default 128
endif # SOC_CH32V303

11
soc/wch/ch32v/qingke_v4f/Kconfig.soc Normal file
View file

@ -0,0 +1,11 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_QINGKE_V4F
bool
select SOC_FAMILY_CH32V
config SOC_SERIES
default "qingke_v4f" if SOC_SERIES_QINGKE_V4F
rsource "Kconfig.soc.*"

9
soc/wch/ch32v/qingke_v4f/Kconfig.soc.ch32v303 Normal file
View file

@ -0,0 +1,9 @@
# Copyright (c) 2025 Bootlin
# SPDX-License-Identifier: Apache-2.0
config SOC_CH32V303
bool
select SOC_SERIES_QINGKE_V4F
config SOC
default "ch32v303" if SOC_CH32V303

42
soc/wch/ch32v/qingke_v4f/pinctrl_soc.h Normal file
View file

@ -0,0 +1,42 @@
/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __PINCTRL_SOC_H__
#define __PINCTRL_SOC_H__
/**
* @brief Type to hold a pin's pinctrl configuration.
*/
struct ch32v303_pinctrl_soc_pin {
uint32_t config: 22;
bool bias_pull_up: 1;
bool bias_pull_down: 1;
bool drive_open_drain: 1;
bool drive_push_pull: 1;
bool output_high: 1;
bool output_low: 1;
uint8_t slew_rate: 2;
};
typedef struct ch32v303_pinctrl_soc_pin pinctrl_soc_pin_t;
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
{ \
.config = DT_PROP_BY_IDX(node_id, prop, idx), \
.bias_pull_up = DT_PROP(node_id, bias_pull_up), \
.bias_pull_down = DT_PROP(node_id, bias_pull_down), \
.drive_open_drain = DT_PROP(node_id, drive_open_drain), \
.drive_push_pull = DT_PROP(node_id, drive_push_pull), \
.output_high = DT_PROP(node_id, output_high), \
.output_low = DT_PROP(node_id, output_low), \
.slew_rate = DT_ENUM_IDX(node_id, slew_rate), \
},
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
Z_PINCTRL_STATE_PIN_INIT)}
#endif

19
soc/wch/ch32v/qingke_v4f/soc_irq.S Normal file
View file

@ -0,0 +1,19 @@
/* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <offsets.h>
#include <zephyr/toolchain.h>
/* Exports */
GTEXT(__soc_is_irq)
GTEXT(__soc_handle_irq)
SECTION_FUNC(exception.other, __soc_is_irq)
csrr a0, mcause
srli a0, a0, 31
ret
SECTION_FUNC(exception.other, __soc_handle_irq)
ret

32
soc/wch/ch32v/qingke_v4f/vector.S Normal file
View file

@ -0,0 +1,32 @@
/*
* Copyright (c) 2024 Michael Hope
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/toolchain.h>
#ifndef CONFIG_VECTOR_TABLE_SIZE
#error "VECTOR_TABLE_SIZE must be defined"
#endif
/* Exports */
GTEXT(__start)
/* Imports */
GTEXT(__initialize)
SECTION_FUNC(vectors, ivt)
.option norvc
/* Jump to 0x08000008, into the main flash zone where j __start is */
lui x5, 0x8000
jr 0x8(x5)
j __start
.rept CONFIG_VECTOR_TABLE_SIZE
.word _isr_wrapper
.endr
SECTION_FUNC(vectors, __start)
li a0, 0xf
csrw mtvec, a0
j __initialize

3
soc/wch/ch32v/soc.yml
View file

@ -16,3 +16,6 @@ family:
- name: qingke-v4b
socs:
- name: ch32v203
- name: qingke-v4f
socs:
- name: ch32v303