From be881d4cf269d3126722ce42e3c198b5960a3f3b Mon Sep 17 00:00:00 2001 From: Kai Vehmanen Date: Wed, 14 Feb 2024 15:23:52 +0200 Subject: [PATCH] arch: xtensa: add isync to interrupt vector On Intel ADSP platforms, additional "isync" is needed in interrupt vector to synchronize icache when core is woken up from deeper sleep state by an interrupt. This is only needed if DSP clock gating is enabled. Signed-off-by: Kai Vehmanen --- arch/xtensa/include/xtensa_asm2_s.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h index 98bba884f12..ad99e279491 100644 --- a/arch/xtensa/include/xtensa_asm2_s.h +++ b/arch/xtensa/include/xtensa_asm2_s.h @@ -604,6 +604,11 @@ _Level\LVL\()Vector: s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET +#ifdef CONFIG_ADSP_IDLE_CLOCK_GATING + /* Needed when waking from low-power waiti state */ + isync +#endif + /* Level "1" is the exception handler, which uses a different * calling convention. No special register holds the * interrupted PS, instead we just assume that the CPU has