riscv: Add device tree support to pulpino

Add simple device tree support for the Pulpino SoC and Zedboard-Pulpino
board port.  This gets the UART info from device tree instead of soc.h

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>

boards/riscv32/zedboard_pulpino/Kconfig.board

@@ -2,4 +2,5 @@
 config BOARD_ZEDBOARD_PULPINO
 	bool "Zedboard pulpino target"
 	depends on SOC_RISCV32_PULPINO
+	select HAS_DTS
 	select BUILD_OUTPUT_S19

boards/riscv32/zedboard_pulpino/zedboard_pulpino.dts

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <pulpino.dtsi>
+
+/ {
+	model = "zedboard_pulpino";
+	compatible = "pulp,zedboard-pulpino";
+
+	aliases {
+		uart-0 = &uart0;
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+	};
+};
+
+&uart0 {
+	status = "ok";
+	current-speed = <115200>;
+};
+

dts/bindings/interrupt-controller/pulpino,event-unit.yaml

@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2018, Linaro Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+---
+title: PULPINO Event Unit
+id: pulp,pulpino-event-unit
+version: 0.1
+
+description: >
+    This binding describes the Pulpino Event Unit
+
+properties:
+  compatible:
+      category: required
+      type: string
+      description: compatible strings
+      constraint: "pulp,pulpino-event-unit"
+      generation: define
+
+  reg:
+      category: required
+      type: int
+      description: mmio register space
+      generation: define
+
+base_label: PULPINO_EVENT_UNIT
+
+"#cells":
+  - irq
+...

dts/riscv32/pulpino.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "pulp,ri5cy", "riscv";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pulp,pulpino-soc", "simple-bus";
+		ranges;
+
+		itim: itim@8000000 {
+			compatible = "pulp,pulpino0itim";
+			reg = <0x0 0x8000>;
+		};
+
+		dtim: dtim@100000 {
+			compatible = "pulp,pulpino-dtim";
+			reg = <0x100000 0x8000>;
+		};
+
+		uart0: uart@1a100000 {
+			compatible = "ns16550";
+			reg = <0x1a100000 0x1000>;
+			label = "UART_0";
+			clock-frequency = <2500000>;
+			interrupts = <24>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		intc: interrupt-controller@1a104000 {
+			#interrupt-cells = <1>;
+			compatible = "pulp,pulpino-event-unit";
+			interrupt-controller;
+			reg = <0x1a104000 0x1000>;
+		};
+	};
+};

soc/riscv32/pulpino/Kconfig.defconfig

@@ -58,26 +58,6 @@ config UART_NS16550_PORT_0
 	bool
 	default y
 
-if UART_NS16550_PORT_0
-
-config UART_NS16550_PORT_0_NAME
-	string
-	default "UART_0"
-
-config UART_NS16550_PORT_0_IRQ_PRI
-	int
-	default 0
-
-config UART_NS16550_PORT_0_BAUD_RATE
-	int
-	default 115200
-
-config UART_NS16550_PORT_0_OPTIONS
-	int
-	default 0
-
-endif # UART_NS16550_PORT_0
-
 endif # UART_NS16550
 
 endif # SOC_RISCV32_PULPINO

soc/riscv32/pulpino/dts.fixup

@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2018, Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* SoC level DTS fixup file */
+
+/*
+ * UART configuration
+ */
+#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR	NS16550_1A100000_BASE_ADDRESS
+#define CONFIG_UART_NS16550_PORT_0_IRQ		NS16550_1A100000_IRQ_0
+#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ	NS16550_1A100000_CLOCK_FREQUENCY
+#define CONFIG_UART_NS16550_PORT_0_BAUD_RATE	NS16550_1A100000_CURRENT_SPEED
+#define CONFIG_UART_NS16550_PORT_0_NAME		NS16550_1A100000_LABEL

soc/riscv32/pulpino/soc.h

@@ -22,7 +22,6 @@
 
 /* IRQ numbers */
 #define PULP_I2C_0_IRQ             23 /* I2C Controller */
-#define PULP_UART_0_IRQ            24 /* Uart Controller */
 #define PULP_GPIO_0_IRQ            25 /* GPIO Controller */
 #define PULP_SPI_0_IRQ             26 /* SPI Controller #0 */
 #define PULP_SPI_1_IRQ             27 /* SPI Controller #1 */
@@ -59,9 +58,6 @@
 #define SOC_ERET                   eret
 
 /* UART configuration */
-#define CONFIG_UART_NS16550_PORT_0_BASE_ADDR     0x1A100000
-#define CONFIG_UART_NS16550_PORT_0_CLK_FREQ      2500000
-#define CONFIG_UART_NS16550_PORT_0_IRQ           PULP_UART_0_IRQ
 #define CONFIG_UART_NS16550_PORT_0_IRQ_PRI       0
 #define CONFIG_UART_NS16550_PORT_0_IRQ_FLAGS     0
 
@@ -72,7 +68,7 @@
 #define PULP_PAD_BASE              0x1A107000
 
 /* IRQ configuration */
-#define PULP_IRQ_BASE              0x1A104000
+#define PULP_IRQ_BASE              PULPINO_EVENT_UNIT_BASE_ADDRESS
 
 #define PULP_IER_ADDR  (PULP_IRQ_BASE + 0x00) /* IRQ Enable Register */
 #define PULP_IPR_ADDR  (PULP_IRQ_BASE + 0x04) /* IRQ Pending Register */