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arch: Add Atmel SAM E70 SoC support

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Added support for Atmel SAM E70 (Cortex-M7) MCU:
- Kconfig files
- device start-up code

Tested on Atmel SMART SAM E70 Xplained board

Origin: Original

Jira: ZEP-978
Change-Id: Ide4fd5dadd94897303090a6507b8d048773b645e
Signed-off-by: Piotr Mienkowski <Piotr.Mienkowski@schmid-telecom.ch>
This commit is contained in:
Piotr Mienkowski 2016-09-27 21:01:54 +02:00 • committed by Anas Nashif
commit be468b0913
11 changed files with 710 additions and 0 deletions
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arch/arm/soc/atmel_sam/Kconfig Normal file
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# Kconfig - Atmel SAM MCU family configuration options
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
# Select SoC Part No. and configuration options
source "arch/arm/soc/atmel_sam/*/Kconfig.soc"

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# Kconfig - Atmel SAM MCU family default configuration options
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
config SOC_FAMILY_SAM
bool
# omit prompt to signify a "hidden" option
default n
config SOC_FAMILY
string
default atmel_sam
depends on SOC_FAMILY_SAM
source "arch/arm/soc/atmel_sam/*/Kconfig.defconfig.series"

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# Kconfig - Atmel SAM MCU series selection
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
source "arch/arm/soc/atmel_sam/*/Kconfig.series"

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# Makefile - Atmel SAM MCU family
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
obj-y += $(SOC_SERIES)/

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arch/arm/soc/atmel_sam/same70/Kconfig.defconfig.series Normal file
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# Kconfig - Atmel SAM E70 MCU series configuration options
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
if SOC_SERIES_SAME70
config SOC_SERIES
string
default same70
config SOC_PART_NUMBER
string
default same70q21 if SOC_PART_NUMBER_SAME70Q21
default same70q20 if SOC_PART_NUMBER_SAME70Q20
default same70q19 if SOC_PART_NUMBER_SAME70Q19
default same70n21 if SOC_PART_NUMBER_SAME70N21
default same70n20 if SOC_PART_NUMBER_SAME70N20
default same70n19 if SOC_PART_NUMBER_SAME70N19
default same70j21 if SOC_PART_NUMBER_SAME70J21
default same70j20 if SOC_PART_NUMBER_SAME70J20
default same70j19 if SOC_PART_NUMBER_SAME70J19
config NUM_IRQ_PRIO_BITS
int
default 3
#
# SAM E70 family has in total 71 peripherals capable of generating interrupts
# (not all Peripheral Identifiers are used).
#
config NUM_IRQS
int
default 71
config SYS_CLOCK_HW_CYCLES_PER_SEC
int
default 300000000
#
# SRAM size and base address
#
config SRAM_BASE_ADDRESS
hex
default 0x20400000
config SRAM_SIZE
int
default 256 if SOC_PART_NUMBER_SAME70Q19 || SOC_PART_NUMBER_SAME70N19 || SOC_PART_NUMBER_SAME70J19
default 384 if SOC_PART_NUMBER_SAME70Q20 || SOC_PART_NUMBER_SAME70N20 || SOC_PART_NUMBER_SAME70J20
default 384 if SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70N21 || SOC_PART_NUMBER_SAME70J21
#
# Flash size and base address
#
config FLASH_BASE_ADDRESS
hex
default 0x00400000
config FLASH_SIZE
int
default 512 if SOC_PART_NUMBER_SAME70Q19 || SOC_PART_NUMBER_SAME70N19 || SOC_PART_NUMBER_SAME70J19
default 1024 if SOC_PART_NUMBER_SAME70Q20 || SOC_PART_NUMBER_SAME70N20 || SOC_PART_NUMBER_SAME70J20
default 2048 if SOC_PART_NUMBER_SAME70Q21 || SOC_PART_NUMBER_SAME70N21 || SOC_PART_NUMBER_SAME70J21
endif # SOC_SERIES_SAME70

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arch/arm/soc/atmel_sam/same70/Kconfig.series Normal file
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# Kconfig - Atmel SAM E70 MCU series
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
config SOC_SERIES_SAME70
bool "Atmel SAME70 MCU"
select CPU_CORTEX_M
select CPU_CORTEX_M7
select SOC_FAMILY_SAM
select CPU_HAS_FPU
select CPU_HAS_SYSTICK
select ASF
select XIP
select SYS_POWER_LOW_POWER_STATE_SUPPORTED
help
Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21

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arch/arm/soc/atmel_sam/same70/Kconfig.soc Normal file
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# Kconfig - Atmel SAM E70 MCU series
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "Atmel SAME70 MCU Selection"
depends on SOC_SERIES_SAME70
config SOC_PART_NUMBER_SAME70Q21
bool "SAME70Q21"
config SOC_PART_NUMBER_SAME70Q20
bool "SAME70Q20"
config SOC_PART_NUMBER_SAME70Q19
bool "SAME70Q19"
config SOC_PART_NUMBER_SAME70N21
bool "SAME70N21"
config SOC_PART_NUMBER_SAME70N20
bool "SAME70N20"
config SOC_PART_NUMBER_SAME70N19
bool "SAME70N19"
config SOC_PART_NUMBER_SAME70J21
bool "SAME70J21"
config SOC_PART_NUMBER_SAME70J20
bool "SAME70J20"
config SOC_PART_NUMBER_SAME70J19
bool "SAME70J19"
endchoice
if SOC_SERIES_SAME70
config SOC_ATMEL_SAME70_EXT_SLCK
bool "Use external crystal oscillator for slow clock"
default n
help
Say y if you want to use external 32 kHz crystal
oscillator to drive the slow clock. Note that this
adds a few seconds to boot time, as the crystal
needs to stabilize after power-up.
Says n if you do not need accurate and precise timers.
The slow clock will be driven by the internal fast
RC oscillator running at 32 kHz.
config SOC_ATMEL_SAME70_EXT_MAINCK
bool "Use external crystal oscillator for main clock"
default n
help
The main clock is being used to drive the PLL, and
thus driving the processor clock.
Say y if you want to use external crystal oscillator
to drive the main clock. Note that this adds about
a second to boot time, as the crystal needs to
stabilize after power-up.
The crystal used here can be from 3 to 20 MHz.
Says n here will use the internal fast RC oscillator
running at 12 MHz.
config SOC_ATMEL_SAME70_MDIV
int "MDIV"
default 2
range 1 4
help
This divisor defines a ratio between processor clock (HCLK)
and master clock (MCK):
MCK = HCLK / MDIV
config SOC_ATMEL_SAME70_PLLA_MULA
int "PLL MULA"
default 24
range 1 62
help
This is the multiplier MULA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting MULA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAME70_PLLA_DIVA
int "PLL DIVA"
default 1
range 1 255
help
This is the divider DIVA used by the PLL.
The processor clock is (MAINCK * (MULA + 1) / DIVA).
Board config file can override this settings
for a particular board.
Setting DIVA=0 would disable PLL at boot, this is currently
not supported.
With default of MULA == 24, and DIVA == 1,
PLL is running at 25 times the main clock frequency.
config SOC_ATMEL_SAME70_WAIT_MODE
bool "Go to Wait mode instead of Sleep mode"
depends on SOC_ATMEL_SAME70_EXT_MAINCK
default y if DEBUG
help
For JTAG debugging CPU clock (HCLK) should not stop. In order
to achieve this, make CPU go to Wait mode instead of Sleep
mode while using external crystal oscillator for main clock.
endif # SOC_SERIES_SAME70

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# Makefile - Atmel SAM E70 MCU series
#
# Copyright (c) 2016 Piotr Mienkowski
# SPDX-License-Identifier: Apache-2.0
#
obj-y += soc.o

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/* linker.ld - Linker command/script file */
/*
* Copyright (c) 2014 Wind River Systems, Inc.
* SPDX-License-Identifier: Apache-2.0
*/
#include <arch/arm/cortex_m/scripts/linker.ld>

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/*
* Copyright (c) 2016 Piotr Mienkowski
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Atmel SAM E70 MCU initialization code
*
* This file provides routines to initialize and support board-level hardware
* for the Atmel SAM E70 MCU.
*/
#include <kernel.h>
#include <device.h>
#include <init.h>
#include <soc.h>
#include <arch/cpu.h>
/* Power Manager Controller */
/*
* PLL clock = Main * (MULA + 1) / DIVA
*
* By default, MULA == 24, DIVA == 1.
* With main crystal running at 12 MHz,
* PLL = 12 * (24 + 1) / 1 = 300 MHz
*
* With Processor Clock prescaler at 1
* Processor Clock (HCLK)=300 MHz.
*/
#define PMC_CKGR_PLLAR_MULA \
(CKGR_PLLAR_MULA(CONFIG_SOC_ATMEL_SAME70_PLLA_MULA))
#define PMC_CKGR_PLLAR_DIVA \
(CKGR_PLLAR_DIVA(CONFIG_SOC_ATMEL_SAME70_PLLA_DIVA))
#if CONFIG_SOC_ATMEL_SAME70_MDIV == 1
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_EQ_PCK
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 2
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV2
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 3
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV3
#elif CONFIG_SOC_ATMEL_SAME70_MDIV == 4
#define SOC_ATMEL_SAME70_MDIV PMC_MCKR_MDIV_PCK_DIV4
#else
#error "Invalid CONFIG_SOC_ATMEL_SAME70_MDIV define value"
#endif
/**
* @brief Setup various clocks on SoC at boot time.
*
* Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
* It is assumed that the relevant registers are at their reset value.
*/
static ALWAYS_INLINE void clock_init(void)
{
uint32_t reg_val;
#ifdef CONFIG_SOC_ATMEL_SAME70_EXT_SLCK
/* Switch slow clock to the external 32 kHz crystal oscillator */
SUPC->SUPC_CR = SUPC_CR_KEY_PASSWD | SUPC_CR_XTALSEL;
/* Wait for oscillator to be stabilized */
while (!(SUPC->SUPC_SR & SUPC_SR_OSCSEL)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAME70_EXT_SLCK */
#ifdef CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK
/*
* Setup main external crystal oscillator
*/
/* Start the external crystal oscillator */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
/* We select maximum setup time. While start up time
* could be shortened this optimization is not deemed
* critical now.
*/
| CKGR_MOR_MOSCXTST(0xFFu)
/* RC OSC must stay on */
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCXTS)) {
;
}
/* Select the external crystal oscillator as main clock source */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCRCEN
| CKGR_MOR_MOSCXTEN;
/* Wait for external oscillator to be selected */
while (!(PMC->PMC_SR & PMC_SR_MOSCSELS)) {
;
}
/* Turn off RC OSC, not used any longer, to save power */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCSEL
| CKGR_MOR_MOSCXTST(0xFFu)
| CKGR_MOR_MOSCXTEN;
/* Wait for RC OSC to be turned off */
while (PMC->PMC_SR & PMC_SR_MOSCRCS) {
;
}
#ifdef CONFIG_SOC_ATMEL_SAME70_WAIT_MODE
/*
* Instruct CPU to enter Wait mode instead of Sleep mode to
* keep Processor Clock (HCLK) and thus be able to debug
* CPU using JTAG
*/
PMC->PMC_FSMR |= PMC_FSMR_LPM;
#endif
#else
/* Attempt to change main fast RC oscillator frequency */
/*
* NOTE: MOSCRCF must be changed only if MOSCRCS is set in the PMC_SR
* register, should normally be the case here
*/
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
/* Set main fast RC oscillator to 12 MHz */
PMC->CKGR_MOR = CKGR_MOR_KEY_PASSWD
| CKGR_MOR_MOSCRCF_12_MHz
| CKGR_MOR_MOSCRCEN;
/* Wait for oscillator to be stabilized */
while (!(PMC->PMC_SR & PMC_SR_MOSCRCS)) {
;
}
#endif /* CONFIG_SOC_ATMEL_SAME70_EXT_MAINCK */
/*
* Setup PLLA
*/
/* Switch MCK (Master Clock) to the main clock first */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_MAIN_CLK;
/* Wait for clock selection to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Setup PLLA */
PMC->CKGR_PLLAR = CKGR_PLLAR_ONE
| PMC_CKGR_PLLAR_MULA
| CKGR_PLLAR_PLLACOUNT(0x3Fu)
| PMC_CKGR_PLLAR_DIVA;
/*
* NOTE: Both MULA and DIVA must be set to a value greater than 0 or
* otherwise PLL will be disabled. In this case we would get stuck in
* the following loop.
*/
/* Wait for PLL lock */
while (!(PMC->PMC_SR & PMC_SR_LOCKA)) {
;
}
/*
* Final setup of the Master Clock
*/
/*
* NOTE: PMC_MCKR must not be programmed in a single write operation.
* If CSS, MDIV or PRES are modified we must wait for MCKRDY bit to be
* set again.
*/
/* Setup prescaler - PLLA Clock / Processor Clock (HCLK) */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_PRES_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_PRES_CLK_1;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Setup divider - Processor Clock (HCLK) / Master Clock (MCK) */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_MDIV_Msk;
PMC->PMC_MCKR = reg_val | SOC_ATMEL_SAME70_MDIV;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
/* Finally select PLL as Master Clock source */
reg_val = PMC->PMC_MCKR & ~PMC_MCKR_CSS_Msk;
PMC->PMC_MCKR = reg_val | PMC_MCKR_CSS_PLLA_CLK;
/* Wait for Master Clock setup to complete */
while (!(PMC->PMC_SR & PMC_SR_MCKRDY)) {
;
}
}
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run at the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int atmel_same70_init(struct device *arg)
{
uint32_t key;
ARG_UNUSED(arg);
key = irq_lock();
/* Clear all faults */
_ScbMemFaultAllFaultsReset();
_ScbBusFaultAllFaultsReset();
_ScbUsageFaultAllFaultsReset();
_ScbHardFaultAllFaultsReset();
/*
* Set FWS (Flash Wait State) value before increasing Master Clock
* (MCK) frequency.
* TODO: set FWS based on the actual MCK frequency and VDDIO value
* rather than maximum supported 150 MHz at standard VDDIO=2.7V
*/
EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
/* Setup system clocks */
clock_init();
/* Install default handler that simply resets the CPU
* if configured in the kernel, NOP otherwise
*/
NMI_INIT();
irq_unlock(key);
return 0;
}
SYS_INIT(atmel_same70_init, PRE_KERNEL_1, 0);

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/*
* Copyright (c) 2016 Piotr Mienkowski
* SPDX-License-Identifier: Apache-2.0
*/
/** @file
* @brief Register access macros for the Atmel SAM E70 MCU.
*
* This file provides register access macros for the Atmel SAM E70 MCU, HAL
* drivers for core peripherals as well as symbols specific to Atmel SAM family.
*/
#ifndef _ATMEL_SAME70_SOC_H_
#define _ATMEL_SAME70_SOC_H_
#define DONT_USE_CMSIS_INIT
#define DONT_USE_PREDEFINED_CORE_HANDLERS
#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
#if defined CONFIG_SOC_PART_NUMBER_SAME70J19
#include <same70j19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J20
#include <same70j20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70J21
#include <same70j21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N19
#include <same70n19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N20
#include <same70n20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70N21
#include <same70n21.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q19
#include <same70q19.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q20
#include <same70q20.h>
#elif defined CONFIG_SOC_PART_NUMBER_SAME70Q21
#include <same70q21.h>
#else
#error Library does not support the specified device.
#endif
/****** Cortex-M7 Processor Exceptions Numbers ******************************/
/** 2 Non Maskable Interrupt */
#define NonMaskableInt_IRQn -14
/** 3 HardFault Interrupt */
#define HardFault_IRQn -13
/** 4 Cortex-M7 Memory Management Interrupt */
#define MemoryManagement_IRQn -12
/** 5 Cortex-M7 Bus Fault Interrupt */
#define BusFault_IRQn -11
/** 6 Cortex-M7 Usage Fault Interrupt */
#define UsageFault_IRQn -10
/** 11 Cortex-M7 SV Call Interrupt */
#define SVCall_IRQn -5
/** 12 Cortex-M7 Debug Monitor Interrupt */
#define DebugMonitor_IRQn -4
/** 14 Cortex-M7 Pend SV Interrupt */
#define PendSV_IRQn -2
/** 15 Cortex-M7 System Tick Interrupt */
#define SysTick_IRQn -1
/****** SAME70 specific Interrupt Numbers ***********************************/
/** 0 SAME70Q21 Supply Controller (SUPC) */
#define SUPC_IRQn 0
/** 1 SAME70Q21 Reset Controller (RSTC) */
#define RSTC_IRQn 1
/** 2 SAME70Q21 Real Time Clock (RTC) */
#define RTC_IRQn 2
/** 3 SAME70Q21 Real Time Timer (RTT) */
#define RTT_IRQn 3
/** 4 SAME70Q21 Watchdog Timer (WDT) */
#define WDT_IRQn 4
/** 5 SAME70Q21 Power Management Controller (PMC) */
#define PMC_IRQn 5
/** 6 SAME70Q21 Enhanced Embedded Flash Controller (EFC) */
#define EFC_IRQn 6
/** 7 SAME70Q21 UART 0 (UART0) */
#define UART0_IRQn 7
/** 8 SAME70Q21 UART 1 (UART1) */
#define UART1_IRQn 8
/** 10 SAME70Q21 Parallel I/O Controller A (PIOA) */
#define PIOA_IRQn 10
/** 11 SAME70Q21 Parallel I/O Controller B (PIOB) */
#define PIOB_IRQn 11
/** 12 SAME70Q21 Parallel I/O Controller C (PIOC) */
#define PIOC_IRQn 12
/** 13 SAME70Q21 USART 0 (USART0) */
#define USART0_IRQn 13
/** 14 SAME70Q21 USART 1 (USART1) */
#define USART1_IRQn 14
/** 15 SAME70Q21 USART 2 (USART2) */
#define USART2_IRQn 15
/** 16 SAME70Q21 Parallel I/O Controller D (PIOD) */
#define PIOD_IRQn 16
/** 17 SAME70Q21 Parallel I/O Controller E (PIOE) */
#define PIOE_IRQn 17
/** 18 SAME70Q21 Multimedia Card Interface (HSMCI) */
#define HSMCI_IRQn 18
/** 19 SAME70Q21 Two Wire Interface 0 HS (TWIHS0) */
#define TWIHS0_IRQn 19
/** 20 SAME70Q21 Two Wire Interface 1 HS (TWIHS1) */
#define TWIHS1_IRQn 20
/** 21 SAME70Q21 Serial Peripheral Interface 0 (SPI0) */
#define SPI0_IRQn 21
/** 22 SAME70Q21 Synchronous Serial Controller (SSC) */
#define SSC_IRQn 22
/** 23 SAME70Q21 Timer/Counter 0 (TC0) */
#define TC0_IRQn 23
/** 24 SAME70Q21 Timer/Counter 1 (TC1) */
#define TC1_IRQn 24
/** 25 SAME70Q21 Timer/Counter 2 (TC2) */
#define TC2_IRQn 25
/** 26 SAME70Q21 Timer/Counter 3 (TC3) */
#define TC3_IRQn 26
/** 27 SAME70Q21 Timer/Counter 4 (TC4) */
#define TC4_IRQn 27
/** 28 SAME70Q21 Timer/Counter 5 (TC5) */
#define TC5_IRQn 28
/** 29 SAME70Q21 Analog Front End 0 (AFEC0) */
#define AFEC0_IRQn 29
/** 30 SAME70Q21 Digital To Analog Converter (DACC) */
#define DACC_IRQn 30
/** 31 SAME70Q21 Pulse Width Modulation 0 (PWM0) */
#define PWM0_IRQn 31
/** 32 SAME70Q21 Integrity Check Monitor (ICM) */
#define ICM_IRQn 32
/** 33 SAME70Q21 Analog Comparator (ACC) */
#define ACC_IRQn 33
/** 34 SAME70Q21 USB Host / Device Controller (USBHS) */
#define USBHS_IRQn 34
/** 35 SAME70Q21 MCAN Controller 0 (MCAN0) */
#define MCAN0_IRQn 35
/** 36 SAME70Q21 MCAN Controller 0 LINE1 (MCAN0) */
#define MCAN0_LINE1_IRQn 36
/** 37 SAME70Q21 MCAN Controller 1 (MCAN1) */
#define MCAN1_IRQn 37
/** 38 SAME70Q21 MCAN Controller 1 LINE1 (MCAN1) */
#define MCAN1_LINE1_IRQn 38
/** 39 SAME70Q21 Ethernet MAC (GMAC) */
#define GMAC_IRQn 39
/** 40 SAME70Q21 Analog Front End 1 (AFEC1) */
#define AFEC1_IRQn 40
/** 41 SAME70Q21 Two Wire Interface 2 HS (TWIHS2) */
#define TWIHS2_IRQn 41
/** 42 SAME70Q21 Serial Peripheral Interface 1 (SPI1) */
#define SPI1_IRQn 42
/** 43 SAME70Q21 Quad I/O Serial Peripheral Interface (QSPI) */
#define QSPI_IRQn 43
/** 44 SAME70Q21 UART 2 (UART2) */
#define UART2_IRQn 44
/** 45 SAME70Q21 UART 3 (UART3) */
#define UART3_IRQn 45
/** 46 SAME70Q21 UART 4 (UART4) */
#define UART4_IRQn 46
/** 47 SAME70Q21 Timer/Counter 6 (TC6) */
#define TC6_IRQn 47
/** 48 SAME70Q21 Timer/Counter 7 (TC7) */
#define TC7_IRQn 48
/** 49 SAME70Q21 Timer/Counter 8 (TC8) */
#define TC8_IRQn 49
/** 50 SAME70Q21 Timer/Counter 9 (TC9) */
#define TC9_IRQn 50
/** 51 SAME70Q21 Timer/Counter 10 (TC10) */
#define TC10_IRQn 51
/** 52 SAME70Q21 Timer/Counter 11 (TC11) */
#define TC11_IRQn 52
/** 56 SAME70Q21 AES (AES) */
#define AES_IRQn 56
/** 57 SAME70Q21 True Random Generator (TRNG) */
#define TRNG_IRQn 57
/** 58 SAME70Q21 DMA (XDMAC) */
#define XDMAC_IRQn 58
/** 59 SAME70Q21 Camera Interface (ISI) */
#define ISI_IRQn 59
/** 60 SAME70Q21 Pulse Width Modulation 1 (PWM1) */
#define PWM1_IRQn 60
/** 62 SAME70Q21 SDRAM Controller (SDRAMC) */
#define SDRAMC_IRQn 62
/** 63 SAME70Q21 Reinforced Secure Watchdog Timer (RSWDT) */
#define RSWDT_IRQn 63
/** Number of peripheral IDs */
#define PERIPH_COUNT_IRQn 64
/** Processor Clock (HCLK) Frequency */
#define SOC_ATMEL_SAM_HCLK_FREQ_HZ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
/** Master Clock (MCK) Frequency */
#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAME70_MDIV)
#endif /* _ATMEL_SAME70_SOC_H_ */