wdt: nxp_s32: use clock control APIs

Use clock control API to retrieve the module's frequency and
update the boards using it to provide the source clocks.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>

boards/arm/s32z270dc2_r52/s32z270dc2_r52.dtsi

@@ -64,26 +64,9 @@
 };
 
 &swt0 {
-	clock-frequency = <48000000>;
 	status = "okay";
 };
 
-&swt1 {
-	clock-frequency = <48000000>;
-};
-
-&swt2 {
-	clock-frequency = <48000000>;
-};
-
-&swt3 {
-	clock-frequency = <48000000>;
-};
-
-&swt4 {
-	clock-frequency = <48000000>;
-};
-
 &emdio {
 	pinctrl-0 = <&emdio_default>;
 	pinctrl-names = "default";

drivers/watchdog/Kconfig.nxp_s32

@@ -1,10 +1,11 @@
-# Copyright 2022 NXP
+# Copyright 2022-2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config WDT_NXP_S32
 	bool "NXP S32 SWT driver"
 	default y
 	depends on DT_HAS_NXP_S32_SWT_ENABLED
+	select CLOCK_CONTROL
 	select NOCACHE_MEMORY
 	help
 	  Enable the Software Watchdog Timer (SWT) driver.

drivers/watchdog/wdt_nxp_s32.c

@@ -1,10 +1,11 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2023 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control.h>
 #include <zephyr/irq.h>
 #include <Swt_Ip.h>
 #include <Swt_Ip_Irq.h>
@@ -16,8 +17,9 @@ LOG_MODULE_REGISTER(swt_nxp_s32);
 #define PARAM_UNUSED	0
 
 struct swt_nxp_s32_config {
-	uint32_t clock_freq;
 	uint8_t instance;
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
 };
 
 struct swt_nxp_s32_data {
@@ -76,18 +78,26 @@ static int swt_nxp_s32_install_timeout(const struct device *dev,
 {
 	const struct swt_nxp_s32_config *config = dev->config;
 	struct swt_nxp_s32_data *data = dev->data;
+	uint32_t clock_rate;
+	int err;
 
 	if (data->timeout_valid) {
 		LOG_ERR("No more timeouts can be installed");
 		return -ENOMEM;
 	}
 
-	data->swt_config.u32TimeoutValue = config->clock_freq / 1000U * cfg->window.max;
+	err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
+	if (err) {
+		LOG_ERR("Failed to get module clock frequency");
+		return err;
+	}
+
+	data->swt_config.u32TimeoutValue = clock_rate / 1000U * cfg->window.max;
 
 	if (cfg->window.min) {
 		data->swt_config.bEnWindow = true;
 		data->swt_config.u32WindowValue =
-			config->clock_freq / 1000U * (cfg->window.max - cfg->window.min);
+			clock_rate / 1000U * (cfg->window.max - cfg->window.min);
 	} else {
 		data->swt_config.bEnWindow = false;
 		data->swt_config.u32WindowValue = 0;
@@ -161,12 +171,26 @@ static const struct wdt_driver_api swt_nxp_s32_driver_api = {
 		},								\
 	};									\
 	static const struct swt_nxp_s32_config swt_nxp_s32_config_##n = {	\
-		.clock_freq = DT_PROP(SWT_NODE(n), clock_frequency),		\
 		.instance = (uint8_t)(RTU_SWT(n)),				\
+		.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(SWT_NODE(n))),	\
+		.clock_subsys = (clock_control_subsys_t)			\
+				DT_CLOCKS_CELL(SWT_NODE(n), name),		\
 	};									\
 										\
 	static int swt_nxp_s32_##n##_init(const struct device *dev)		\
 	{									\
+		const struct swt_nxp_s32_config *config = dev->config;		\
+		int err;							\
+										\
+		if (!device_is_ready(config->clock_dev)) {			\
+			return -ENODEV;						\
+		}								\
+										\
+		err = clock_control_on(config->clock_dev, config->clock_subsys);\
+		if (err) {							\
+			return err;						\
+		}								\
+										\
 		IRQ_CONNECT(DT_IRQN(SWT_NODE(n)),				\
 			    DT_IRQ(SWT_NODE(n), priority),			\
 			    Swt_Ip_IrqHandler,					\

dts/arm/nxp/nxp_s32z27x_rtu0_r52.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2023 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,6 +48,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76000000 0x10000>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -55,6 +56,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76010000 0x10000>;
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -62,6 +64,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76220000 0x10000>;
 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -69,6 +72,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76230000 0x10000>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -76,6 +80,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76140000 0x10000>;
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 	};

dts/arm/nxp/nxp_s32z27x_rtu1_r52.dtsi

@@ -1,5 +1,5 @@
 /*
- * Copyright 2022 NXP
+ * Copyright 2022-2023 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -48,6 +48,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76800000 0x10000>;
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -55,6 +56,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76810000 0x10000>;
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -62,6 +64,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76a20000 0x10000>;
 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -69,6 +72,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76a30000 0x10000>;
 			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 
@@ -76,6 +80,7 @@
 			compatible = "nxp,s32-swt";
 			reg = <0x76940000 0x10000>;
 			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_FIRC_CLK>;
 			status = "disabled";
 		};
 	};

dts/bindings/watchdog/nxp,s32-swt.yaml

@@ -1,4 +1,4 @@
-# Copyright 2022 NXP
+# Copyright 2022-2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: Software Watchdog Timer (SWT)
@@ -14,7 +14,5 @@ properties:
   interrupts:
     required: true
 
-  clock-frequency:
+  clocks:
-    type: int
     required: true
-    description: Software Watchdog Timer module clock frequency, in Hz.