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driver: gpio: dw: convert to DT_INST defines

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Convert driver to use DT_INST_ defines.  The preferred defines for
drivers are DT_INST_.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala 2020-02-13 13:25:58 -06:00 • committed by Kumar Gala
commit bdcf87956b
8 changed files with 65 additions and 174 deletions
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52
drivers/gpio/Kconfig.dw
View file

@ -34,12 +34,6 @@ config GPIO_DW_0
help
Include Designware GPIO driver
config GPIO_DW_0_NAME
string "Driver name"
depends on GPIO_DW_0
depends on !HAS_DTS
default "GPIO_0"
config GPIO_DW_0_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
depends on GPIO_DW_CLOCK_GATE && GPIO_DW_0
@ -64,24 +58,11 @@ config GPIO_DW_0_IRQ_SHARED
endchoice
config GPIO_DW_0_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT
depends on !HAS_DTS
help
IRQ priority
config GPIO_DW_1
bool "Designware GPIO block 1"
help
Include Designware GPIO driver
config GPIO_DW_1_NAME
string "Driver name"
depends on GPIO_DW_1
depends on !HAS_DTS
default "GPIO_1"
config GPIO_DW_1_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
depends on GPIO_DW_CLOCK_GATE && GPIO_DW_1
@ -106,24 +87,11 @@ config GPIO_DW_1_IRQ_SHARED
endchoice
config GPIO_DW_1_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT
depends on !HAS_DTS
help
IRQ priority
config GPIO_DW_2
bool "Designware GPIO block 1"
help
Include Designware GPIO driver
config GPIO_DW_2_NAME
string "Driver name"
depends on GPIO_DW_2
depends on !HAS_DTS
default "GPIO_2"
config GPIO_DW_2_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
depends on GPIO_DW_CLOCK_GATE && GPIO_DW_2
@ -148,24 +116,11 @@ config GPIO_DW_2_IRQ_SHARED
endchoice
config GPIO_DW_2_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_DW_2 && GPIO_DW_2_IRQ_DIRECT
depends on !HAS_DTS
help
IRQ priority
config GPIO_DW_3
bool "Designware GPIO block 1"
help
Include Designware GPIO driver
config GPIO_DW_3_NAME
string "Driver name"
depends on GPIO_DW_3
depends on !HAS_DTS
default "GPIO_3"
config GPIO_DW_3_CLOCK_GATE_SUBSYS
int "Clock controller's subsystem"
depends on GPIO_DW_CLOCK_GATE && GPIO_DW_3
@ -190,11 +145,4 @@ config GPIO_DW_3_IRQ_SHARED
endchoice
config GPIO_DW_3_IRQ_PRI
int "Controller interrupt priority"
depends on GPIO_DW_3 && GPIO_DW_3_IRQ_DIRECT
depends on !HAS_DTS
help
IRQ priority
endif # GPIO_DW

104
drivers/gpio/gpio_dw.c
View file

@ -587,12 +587,12 @@ static const struct gpio_dw_config gpio_config_0 = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_SNPS_DESIGNWARE_GPIO_NGPIOS),
},
#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
.irq_num = DT_GPIO_DW_0_IRQ,
.irq_num = DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0,
#endif
.bits = DT_GPIO_DW_0_BITS,
.bits = DT_INST_0_SNPS_DESIGNWARE_GPIO_BITS,
.config_func = gpio_config_0_irq,
#ifdef CONFIG_GPIO_DW_0_IRQ_SHARED
.shared_irq_dev_name = DT_GPIO_DW_0_IRQ_SHARED_NAME,
.shared_irq_dev_name = DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
#endif
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS),
@ -600,30 +600,32 @@ static const struct gpio_dw_config gpio_config_0 = {
};
static struct gpio_dw_runtime gpio_0_runtime = {
.base_addr = DT_GPIO_DW_0_BASE_ADDR,
.base_addr = DT_INST_0_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
gpio_dw_device_ctrl, &gpio_0_runtime, &gpio_config_0,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
DEVICE_DEFINE(gpio_dw_0, DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_0_runtime,
&gpio_config_0, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#else
DEVICE_AND_API_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
&gpio_0_runtime, &gpio_config_0,
DEVICE_AND_API_INIT(gpio_dw_0, DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, &gpio_0_runtime, &gpio_config_0,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#endif
static void gpio_config_0_irq(struct device *port)
{
#if (DT_GPIO_DW_0_IRQ > 0)
#if (DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
IRQ_CONNECT(DT_GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_0), DT_GPIO_DW_0_IRQ_FLAGS);
IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0,
DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
DEVICE_GET(gpio_dw_0),
DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
struct device *shared_irq_dev;
@ -649,13 +651,13 @@ static const struct gpio_dw_config gpio_dw_config_1 = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_SNPS_DESIGNWARE_GPIO_NGPIOS),
},
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
.irq_num = DT_GPIO_DW_1_IRQ,
.irq_num = DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0,
#endif
.bits = DT_GPIO_DW_1_BITS,
.bits = DT_INST_1_SNPS_DESIGNWARE_GPIO_BITS,
.config_func = gpio_config_1_irq,
#ifdef CONFIG_GPIO_DW_1_IRQ_SHARED
.shared_irq_dev_name = DT_GPIO_DW_1_IRQ_SHARED_NAME,
.shared_irq_dev_name = DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
#endif
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS),
@ -663,29 +665,31 @@ static const struct gpio_dw_config gpio_dw_config_1 = {
};
static struct gpio_dw_runtime gpio_1_runtime = {
.base_addr = DT_GPIO_DW_1_BASE_ADDR,
.base_addr = DT_INST_1_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
gpio_dw_device_ctrl, &gpio_1_runtime, &gpio_dw_config_1,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
DEVICE_DEFINE(gpio_dw_1, DT_INST_1_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_1_runtime,
&gpio_dw_config_1, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#else
DEVICE_AND_API_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
&gpio_1_runtime, &gpio_dw_config_1,
DEVICE_AND_API_INIT(gpio_dw_1, DT_INST_1_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, &gpio_1_runtime, &gpio_dw_config_1,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#endif
static void gpio_config_1_irq(struct device *port)
{
#if (DT_GPIO_DW_1_IRQ > 0)
#if (DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
IRQ_CONNECT(DT_GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS);
IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0,
DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
DEVICE_GET(gpio_dw_1),
DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
struct device *shared_irq_dev;
@ -710,13 +714,13 @@ static const struct gpio_dw_config gpio_dw_config_2 = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_SNPS_DESIGNWARE_GPIO_NGPIOS),
},
#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
.irq_num = DT_GPIO_DW_2_IRQ,
.irq_num = DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0,
#endif
.bits = DT_GPIO_DW_2_BITS,
.bits = DT_INST_2_SNPS_DESIGNWARE_GPIO_BITS,
.config_func = gpio_config_2_irq,
#ifdef CONFIG_GPIO_DW_2_IRQ_SHARED
.shared_irq_dev_name = DT_GPIO_DW_2_IRQ_SHARED_NAME,
.shared_irq_dev_name = DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
#endif
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_2_CLOCK_GATE_SUBSYS),
@ -724,29 +728,31 @@ static const struct gpio_dw_config gpio_dw_config_2 = {
};
static struct gpio_dw_runtime gpio_2_runtime = {
.base_addr = DT_GPIO_DW_2_BASE_ADDR,
.base_addr = DT_INST_2_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize,
gpio_dw_device_ctrl, &gpio_2_runtime, &gpio_dw_config_2,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
DEVICE_DEFINE(gpio_dw_2, DT_INST_2_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_2_runtime,
&gpio_dw_config_2, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#else
DEVICE_AND_API_INIT(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize,
&gpio_2_runtime, &gpio_dw_config_2,
DEVICE_AND_API_INIT(gpio_dw_2, DT_INST_2_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, &gpio_2_runtime, &gpio_dw_config_2,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#endif
static void gpio_config_2_irq(struct device *port)
{
#if (DT_GPIO_DW_2_IRQ > 0)
#if (DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
IRQ_CONNECT(DT_GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_2), GPIO_DW_2_IRQ_FLAGS);
IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0,
DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
DEVICE_GET(gpio_dw_2),
DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_2_IRQ_SHARED)
struct device *shared_irq_dev;
@ -771,13 +777,13 @@ static const struct gpio_dw_config gpio_dw_config_3 = {
.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_SNPS_DESIGNWARE_GPIO_NGPIOS),
},
#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
.irq_num = DT_GPIO_DW_3_IRQ,
.irq_num = DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0,
#endif
.bits = DT_GPIO_DW_3_BITS,
.bits = DT_INST_3_SNPS_DESIGNWARE_GPIO_BITS,
.config_func = gpio_config_3_irq,
#ifdef CONFIG_GPIO_DW_3_IRQ_SHARED
.shared_irq_dev_name = DT_GPIO_DW_3_IRQ_SHARED_NAME,
.shared_irq_dev_name = DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
#endif
#ifdef CONFIG_GPIO_DW_CLOCK_GATE
.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_3_CLOCK_GATE_SUBSYS),
@ -785,29 +791,31 @@ static const struct gpio_dw_config gpio_dw_config_3 = {
};
static struct gpio_dw_runtime gpio_3_runtime = {
.base_addr = DT_GPIO_DW_3_BASE_ADDR,
.base_addr = DT_INST_3_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
};
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
DEVICE_DEFINE(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize,
gpio_dw_device_ctrl, &gpio_3_runtime, &gpio_dw_config_3,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
DEVICE_DEFINE(gpio_dw_3, DT_INST_3_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_3_runtime,
&gpio_dw_config_3, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#else
DEVICE_AND_API_INIT(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize,
&gpio_3_runtime, &gpio_dw_config_3,
DEVICE_AND_API_INIT(gpio_dw_3, DT_INST_3_SNPS_DESIGNWARE_GPIO_LABEL,
gpio_dw_initialize, &gpio_3_runtime, &gpio_dw_config_3,
POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
&api_funcs);
#endif
static void gpio_config_3_irq(struct device *port)
{
#if (DT_GPIO_DW_3_IRQ > 0)
#if (DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
const struct gpio_dw_config *config = port->config->config_info;
#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
IRQ_CONNECT(DT_GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr,
DEVICE_GET(gpio_dw_3), GPIO_DW_3_IRQ_FLAGS);
IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0,
DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
DEVICE_GET(gpio_dw_3),
DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
irq_enable(config->irq_num);
#elif defined(CONFIG_GPIO_DW_3_IRQ_SHARED)
struct device *shared_irq_dev;

7
soc/arc/snps_arc_hsdk/dts_fixup.h
View file

@ -19,12 +19,7 @@
/*
* GPIO configuration
*/
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0003000_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0003000_BITS
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0003000_LABEL
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
/*
* SPI configuration

15
soc/arc/snps_emsdp/dts_fixup.h
View file

@ -26,18 +26,7 @@
/*
* GPIO configuration
*/
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
#define DT_GPIO_DW_1_IRQ_FLAGS 0
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
#define DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
/* End of SoC Level DTS fixup file */

28
soc/arc/snps_emsk/dts_fixup.h
View file

@ -39,30 +39,10 @@
/*
* GPIO configuration
*/
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
#define DT_GPIO_DW_2_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS
#define DT_GPIO_DW_2_BITS DT_SNPS_DESIGNWARE_GPIO_F0002018_BITS
#define CONFIG_GPIO_DW_2_NAME DT_SNPS_DESIGNWARE_GPIO_F0002018_LABEL
#define DT_GPIO_DW_2_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0
#define CONFIG_GPIO_DW_2_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0_PRIORITY
#define DT_GPIO_DW_3_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS
#define DT_GPIO_DW_3_BITS DT_SNPS_DESIGNWARE_GPIO_F0002024_BITS
#define CONFIG_GPIO_DW_3_NAME DT_SNPS_DESIGNWARE_GPIO_F0002024_LABEL
#define DT_GPIO_DW_3_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0
#define CONFIG_GPIO_DW_3_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0_PRIORITY
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
#define DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
#define DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
#define DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
/*
* SPI configuration

19
soc/arc/snps_emsk/soc.h
View file

@ -62,25 +62,6 @@
#define DT_I2C_1_BASE_ADDR 0xF0005000
#define DT_I2C_1_IRQ_FLAGS 0
/* GPIO */
#define DT_GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
#define DT_GPIO_DW_0_BITS 32
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
#define DT_GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
#define DT_GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
#define DT_GPIO_DW_1_BITS 9 /* 9 LEDs on board */
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
#define DT_GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
#define DT_GPIO_DW_2_BITS 32
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
#define DT_GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
#define DT_GPIO_DW_3_BITS 12
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
/* SPI */
#define DT_SPI_DW_IRQ_FLAGS 0

12
soc/xtensa/intel_s1000/dts_fixup.h
View file

@ -58,17 +58,7 @@
#define DT_SPI_DW_0_IRQ_PRI \
DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_BASE_ADDR \
DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
#define DT_GPIO_DW_0_BITS \
DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
#define DT_GPIO_DW_0_IRQ \
DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0
#define CONFIG_GPIO_DW_0_IRQ_PRI \
DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
#define DT_GPIO_DW_0_IRQ_FLAGS 0
#define CONFIG_GPIO_DW_0_NAME \
DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
#define DT_PINMUX_BASE_ADDR \
DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS

2
tests/boards/intel_s1000_crb/src/gpio_test.c
View file

@ -36,7 +36,7 @@
#define GPIO_OUT_PIN 23
#define GPIO_INT_PIN 24
#define GPIO_NAME "GPIO_"
#define GPIO_DRV_NAME CONFIG_GPIO_DW_0_NAME
#define GPIO_DRV_NAME DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL
/* size of stack area used by each thread */
#define STACKSIZE 1024