driver: gpio: dw: convert to DT_INST defines
Convert driver to use DT_INST_ defines. The preferred defines for drivers are DT_INST_. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
parent
5d332c974e
commit
bdcf87956b
8 changed files with 65 additions and 174 deletions
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@ -34,12 +34,6 @@ config GPIO_DW_0
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help
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Include Designware GPIO driver
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config GPIO_DW_0_NAME
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string "Driver name"
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depends on GPIO_DW_0
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depends on !HAS_DTS
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default "GPIO_0"
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config GPIO_DW_0_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_0
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@ -64,24 +58,11 @@ config GPIO_DW_0_IRQ_SHARED
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endchoice
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config GPIO_DW_0_IRQ_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_0 && GPIO_DW_0_IRQ_DIRECT
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depends on !HAS_DTS
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help
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IRQ priority
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config GPIO_DW_1
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bool "Designware GPIO block 1"
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help
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Include Designware GPIO driver
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config GPIO_DW_1_NAME
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string "Driver name"
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depends on GPIO_DW_1
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depends on !HAS_DTS
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default "GPIO_1"
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config GPIO_DW_1_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_1
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@ -106,24 +87,11 @@ config GPIO_DW_1_IRQ_SHARED
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endchoice
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config GPIO_DW_1_IRQ_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_1 && GPIO_DW_1_IRQ_DIRECT
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depends on !HAS_DTS
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help
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IRQ priority
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config GPIO_DW_2
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bool "Designware GPIO block 1"
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help
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Include Designware GPIO driver
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config GPIO_DW_2_NAME
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string "Driver name"
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depends on GPIO_DW_2
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depends on !HAS_DTS
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default "GPIO_2"
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config GPIO_DW_2_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_2
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@ -148,24 +116,11 @@ config GPIO_DW_2_IRQ_SHARED
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endchoice
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config GPIO_DW_2_IRQ_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_2 && GPIO_DW_2_IRQ_DIRECT
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depends on !HAS_DTS
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help
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IRQ priority
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config GPIO_DW_3
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bool "Designware GPIO block 1"
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help
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Include Designware GPIO driver
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config GPIO_DW_3_NAME
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string "Driver name"
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depends on GPIO_DW_3
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depends on !HAS_DTS
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default "GPIO_3"
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config GPIO_DW_3_CLOCK_GATE_SUBSYS
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int "Clock controller's subsystem"
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depends on GPIO_DW_CLOCK_GATE && GPIO_DW_3
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@ -190,11 +145,4 @@ config GPIO_DW_3_IRQ_SHARED
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endchoice
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config GPIO_DW_3_IRQ_PRI
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int "Controller interrupt priority"
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depends on GPIO_DW_3 && GPIO_DW_3_IRQ_DIRECT
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depends on !HAS_DTS
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help
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IRQ priority
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endif # GPIO_DW
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@ -587,12 +587,12 @@ static const struct gpio_dw_config gpio_config_0 = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_SNPS_DESIGNWARE_GPIO_NGPIOS),
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},
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#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
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.irq_num = DT_GPIO_DW_0_IRQ,
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.irq_num = DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0,
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#endif
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.bits = DT_GPIO_DW_0_BITS,
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.bits = DT_INST_0_SNPS_DESIGNWARE_GPIO_BITS,
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.config_func = gpio_config_0_irq,
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#ifdef CONFIG_GPIO_DW_0_IRQ_SHARED
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.shared_irq_dev_name = DT_GPIO_DW_0_IRQ_SHARED_NAME,
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.shared_irq_dev_name = DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_0_CLOCK_GATE_SUBSYS),
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@ -600,30 +600,32 @@ static const struct gpio_dw_config gpio_config_0 = {
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};
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static struct gpio_dw_runtime gpio_0_runtime = {
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.base_addr = DT_GPIO_DW_0_BASE_ADDR,
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.base_addr = DT_INST_0_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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DEVICE_DEFINE(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
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gpio_dw_device_ctrl, &gpio_0_runtime, &gpio_config_0,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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DEVICE_DEFINE(gpio_dw_0, DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_0_runtime,
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&gpio_config_0, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#else
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DEVICE_AND_API_INIT(gpio_dw_0, CONFIG_GPIO_DW_0_NAME, gpio_dw_initialize,
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&gpio_0_runtime, &gpio_config_0,
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DEVICE_AND_API_INIT(gpio_dw_0, DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, &gpio_0_runtime, &gpio_config_0,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#endif
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static void gpio_config_0_irq(struct device *port)
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{
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#if (DT_GPIO_DW_0_IRQ > 0)
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#if (DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
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const struct gpio_dw_config *config = port->config->config_info;
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#ifdef CONFIG_GPIO_DW_0_IRQ_DIRECT
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IRQ_CONNECT(DT_GPIO_DW_0_IRQ, CONFIG_GPIO_DW_0_IRQ_PRI, gpio_dw_isr,
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DEVICE_GET(gpio_dw_0), DT_GPIO_DW_0_IRQ_FLAGS);
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IRQ_CONNECT(DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0,
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DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
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DEVICE_GET(gpio_dw_0),
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DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
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irq_enable(config->irq_num);
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#elif defined(CONFIG_GPIO_DW_0_IRQ_SHARED)
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struct device *shared_irq_dev;
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@ -649,13 +651,13 @@ static const struct gpio_dw_config gpio_dw_config_1 = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_SNPS_DESIGNWARE_GPIO_NGPIOS),
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},
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#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
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.irq_num = DT_GPIO_DW_1_IRQ,
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.irq_num = DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0,
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#endif
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.bits = DT_GPIO_DW_1_BITS,
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.bits = DT_INST_1_SNPS_DESIGNWARE_GPIO_BITS,
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.config_func = gpio_config_1_irq,
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#ifdef CONFIG_GPIO_DW_1_IRQ_SHARED
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.shared_irq_dev_name = DT_GPIO_DW_1_IRQ_SHARED_NAME,
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.shared_irq_dev_name = DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_1_CLOCK_GATE_SUBSYS),
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@ -663,29 +665,31 @@ static const struct gpio_dw_config gpio_dw_config_1 = {
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};
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static struct gpio_dw_runtime gpio_1_runtime = {
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.base_addr = DT_GPIO_DW_1_BASE_ADDR,
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.base_addr = DT_INST_1_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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DEVICE_DEFINE(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
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gpio_dw_device_ctrl, &gpio_1_runtime, &gpio_dw_config_1,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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DEVICE_DEFINE(gpio_dw_1, DT_INST_1_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_1_runtime,
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&gpio_dw_config_1, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#else
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DEVICE_AND_API_INIT(gpio_dw_1, CONFIG_GPIO_DW_1_NAME, gpio_dw_initialize,
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&gpio_1_runtime, &gpio_dw_config_1,
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DEVICE_AND_API_INIT(gpio_dw_1, DT_INST_1_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, &gpio_1_runtime, &gpio_dw_config_1,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#endif
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static void gpio_config_1_irq(struct device *port)
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{
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#if (DT_GPIO_DW_1_IRQ > 0)
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#if (DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
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const struct gpio_dw_config *config = port->config->config_info;
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#ifdef CONFIG_GPIO_DW_1_IRQ_DIRECT
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IRQ_CONNECT(DT_GPIO_DW_1_IRQ, CONFIG_GPIO_DW_1_IRQ_PRI, gpio_dw_isr,
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DEVICE_GET(gpio_dw_1), GPIO_DW_1_IRQ_FLAGS);
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IRQ_CONNECT(DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0,
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DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
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DEVICE_GET(gpio_dw_1),
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DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
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irq_enable(config->irq_num);
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#elif defined(CONFIG_GPIO_DW_1_IRQ_SHARED)
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struct device *shared_irq_dev;
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@ -710,13 +714,13 @@ static const struct gpio_dw_config gpio_dw_config_2 = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_SNPS_DESIGNWARE_GPIO_NGPIOS),
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},
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#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
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.irq_num = DT_GPIO_DW_2_IRQ,
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.irq_num = DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0,
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#endif
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.bits = DT_GPIO_DW_2_BITS,
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.bits = DT_INST_2_SNPS_DESIGNWARE_GPIO_BITS,
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.config_func = gpio_config_2_irq,
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#ifdef CONFIG_GPIO_DW_2_IRQ_SHARED
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.shared_irq_dev_name = DT_GPIO_DW_2_IRQ_SHARED_NAME,
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.shared_irq_dev_name = DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_2_CLOCK_GATE_SUBSYS),
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@ -724,29 +728,31 @@ static const struct gpio_dw_config gpio_dw_config_2 = {
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};
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static struct gpio_dw_runtime gpio_2_runtime = {
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.base_addr = DT_GPIO_DW_2_BASE_ADDR,
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.base_addr = DT_INST_2_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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DEVICE_DEFINE(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize,
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gpio_dw_device_ctrl, &gpio_2_runtime, &gpio_dw_config_2,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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DEVICE_DEFINE(gpio_dw_2, DT_INST_2_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_2_runtime,
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&gpio_dw_config_2, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#else
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DEVICE_AND_API_INIT(gpio_dw_2, CONFIG_GPIO_DW_2_NAME, gpio_dw_initialize,
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&gpio_2_runtime, &gpio_dw_config_2,
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DEVICE_AND_API_INIT(gpio_dw_2, DT_INST_2_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, &gpio_2_runtime, &gpio_dw_config_2,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#endif
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static void gpio_config_2_irq(struct device *port)
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{
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#if (DT_GPIO_DW_2_IRQ > 0)
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#if (DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
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const struct gpio_dw_config *config = port->config->config_info;
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#ifdef CONFIG_GPIO_DW_2_IRQ_DIRECT
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IRQ_CONNECT(DT_GPIO_DW_2_IRQ, CONFIG_GPIO_DW_2_IRQ_PRI, gpio_dw_isr,
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DEVICE_GET(gpio_dw_2), GPIO_DW_2_IRQ_FLAGS);
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IRQ_CONNECT(DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0,
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DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
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DEVICE_GET(gpio_dw_2),
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DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
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irq_enable(config->irq_num);
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#elif defined(CONFIG_GPIO_DW_2_IRQ_SHARED)
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struct device *shared_irq_dev;
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@ -771,13 +777,13 @@ static const struct gpio_dw_config gpio_dw_config_3 = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_SNPS_DESIGNWARE_GPIO_NGPIOS),
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},
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#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
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.irq_num = DT_GPIO_DW_3_IRQ,
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.irq_num = DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0,
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#endif
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.bits = DT_GPIO_DW_3_BITS,
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.bits = DT_INST_3_SNPS_DESIGNWARE_GPIO_BITS,
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.config_func = gpio_config_3_irq,
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#ifdef CONFIG_GPIO_DW_3_IRQ_SHARED
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.shared_irq_dev_name = DT_GPIO_DW_3_IRQ_SHARED_NAME,
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.shared_irq_dev_name = DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_SHARED_NAME,
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#endif
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#ifdef CONFIG_GPIO_DW_CLOCK_GATE
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.clock_data = UINT_TO_POINTER(CONFIG_GPIO_DW_3_CLOCK_GATE_SUBSYS),
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@ -785,29 +791,31 @@ static const struct gpio_dw_config gpio_dw_config_3 = {
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};
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static struct gpio_dw_runtime gpio_3_runtime = {
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.base_addr = DT_GPIO_DW_3_BASE_ADDR,
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.base_addr = DT_INST_3_SNPS_DESIGNWARE_GPIO_BASE_ADDRESS,
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};
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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DEVICE_DEFINE(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize,
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gpio_dw_device_ctrl, &gpio_3_runtime, &gpio_dw_config_3,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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DEVICE_DEFINE(gpio_dw_3, DT_INST_3_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, gpio_dw_device_ctrl, &gpio_3_runtime,
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&gpio_dw_config_3, POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#else
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DEVICE_AND_API_INIT(gpio_dw_3, CONFIG_GPIO_DW_3_NAME, gpio_dw_initialize,
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&gpio_3_runtime, &gpio_dw_config_3,
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DEVICE_AND_API_INIT(gpio_dw_3, DT_INST_3_SNPS_DESIGNWARE_GPIO_LABEL,
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gpio_dw_initialize, &gpio_3_runtime, &gpio_dw_config_3,
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POST_KERNEL, CONFIG_GPIO_DW_INIT_PRIORITY,
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&api_funcs);
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#endif
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static void gpio_config_3_irq(struct device *port)
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{
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#if (DT_GPIO_DW_3_IRQ > 0)
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#if (DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0 > 0)
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const struct gpio_dw_config *config = port->config->config_info;
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#ifdef CONFIG_GPIO_DW_3_IRQ_DIRECT
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IRQ_CONNECT(DT_GPIO_DW_3_IRQ, CONFIG_GPIO_DW_3_IRQ_PRI, gpio_dw_isr,
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DEVICE_GET(gpio_dw_3), GPIO_DW_3_IRQ_FLAGS);
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IRQ_CONNECT(DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0,
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DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_PRIORITY, gpio_dw_isr,
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DEVICE_GET(gpio_dw_3),
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DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS);
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irq_enable(config->irq_num);
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#elif defined(CONFIG_GPIO_DW_3_IRQ_SHARED)
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struct device *shared_irq_dev;
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@ -19,12 +19,7 @@
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/*
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* GPIO configuration
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*/
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#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0003000_BASE_ADDRESS
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#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0003000_BITS
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#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0003000_LABEL
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#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0
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#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0003000_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
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/*
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* SPI configuration
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@ -26,18 +26,7 @@
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/*
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* GPIO configuration
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*/
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#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
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#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
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#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
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#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
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#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
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#define DT_GPIO_DW_0_IRQ_FLAGS 0
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#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
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#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
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#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
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#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
|
||||
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_DW_1_IRQ_FLAGS 0
|
||||
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
#define DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
|
||||
/* End of SoC Level DTS fixup file */
|
||||
|
|
|
@ -39,30 +39,10 @@
|
|||
/*
|
||||
* GPIO configuration
|
||||
*/
|
||||
#define DT_GPIO_DW_0_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002000_BASE_ADDRESS
|
||||
#define DT_GPIO_DW_0_BITS DT_SNPS_DESIGNWARE_GPIO_F0002000_BITS
|
||||
#define CONFIG_GPIO_DW_0_NAME DT_SNPS_DESIGNWARE_GPIO_F0002000_LABEL
|
||||
#define DT_GPIO_DW_0_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0
|
||||
#define CONFIG_GPIO_DW_0_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002000_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_DW_0_IRQ_FLAGS 0
|
||||
|
||||
#define DT_GPIO_DW_1_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F000200C_BASE_ADDRESS
|
||||
#define DT_GPIO_DW_1_BITS DT_SNPS_DESIGNWARE_GPIO_F000200C_BITS
|
||||
#define CONFIG_GPIO_DW_1_NAME DT_SNPS_DESIGNWARE_GPIO_F000200C_LABEL
|
||||
#define DT_GPIO_DW_1_IRQ DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0
|
||||
#define CONFIG_GPIO_DW_1_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F000200C_IRQ_0_PRIORITY
|
||||
|
||||
#define DT_GPIO_DW_2_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002018_BASE_ADDRESS
|
||||
#define DT_GPIO_DW_2_BITS DT_SNPS_DESIGNWARE_GPIO_F0002018_BITS
|
||||
#define CONFIG_GPIO_DW_2_NAME DT_SNPS_DESIGNWARE_GPIO_F0002018_LABEL
|
||||
#define DT_GPIO_DW_2_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0
|
||||
#define CONFIG_GPIO_DW_2_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002018_IRQ_0_PRIORITY
|
||||
|
||||
#define DT_GPIO_DW_3_BASE_ADDR DT_SNPS_DESIGNWARE_GPIO_F0002024_BASE_ADDRESS
|
||||
#define DT_GPIO_DW_3_BITS DT_SNPS_DESIGNWARE_GPIO_F0002024_BITS
|
||||
#define CONFIG_GPIO_DW_3_NAME DT_SNPS_DESIGNWARE_GPIO_F0002024_LABEL
|
||||
#define DT_GPIO_DW_3_IRQ DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0
|
||||
#define CONFIG_GPIO_DW_3_IRQ_PRI DT_SNPS_DESIGNWARE_GPIO_F0002024_IRQ_0_PRIORITY
|
||||
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
#define DT_INST_1_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
#define DT_INST_2_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
#define DT_INST_3_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
|
||||
/*
|
||||
* SPI configuration
|
||||
|
|
|
@ -62,25 +62,6 @@
|
|||
#define DT_I2C_1_BASE_ADDR 0xF0005000
|
||||
#define DT_I2C_1_IRQ_FLAGS 0
|
||||
|
||||
|
||||
/* GPIO */
|
||||
#define DT_GPIO_DW_0_BASE_ADDR 0xF0002000 /* GPIO 0 : PORTA */
|
||||
#define DT_GPIO_DW_0_BITS 32
|
||||
#define GPIO_DW_PORT_0_INT_MASK 0 /* n/a */
|
||||
#define DT_GPIO_DW_0_IRQ_FLAGS 0 /* Defaults */
|
||||
|
||||
#define DT_GPIO_DW_1_BASE_ADDR 0xF000200C /* GPIO 1 : PORTB */
|
||||
#define DT_GPIO_DW_1_BITS 9 /* 9 LEDs on board */
|
||||
#define GPIO_DW_PORT_1_INT_MASK 0 /* n/a */
|
||||
|
||||
#define DT_GPIO_DW_2_BASE_ADDR 0xF0002018 /* GPIO 2 : PORTC */
|
||||
#define DT_GPIO_DW_2_BITS 32
|
||||
#define GPIO_DW_PORT_2_INT_MASK 0 /* n/a */
|
||||
|
||||
#define DT_GPIO_DW_3_BASE_ADDR 0xF0002024 /* GPIO 3 : PORTD */
|
||||
#define DT_GPIO_DW_3_BITS 12
|
||||
#define GPIO_DW_PORT_3_INT_MASK 0 /* n/a */
|
||||
|
||||
/* SPI */
|
||||
#define DT_SPI_DW_IRQ_FLAGS 0
|
||||
|
||||
|
|
|
@ -58,17 +58,7 @@
|
|||
#define DT_SPI_DW_0_IRQ_PRI \
|
||||
DT_SNPS_DESIGNWARE_SPI_E000_IRQ_0_PRIORITY
|
||||
|
||||
#define DT_GPIO_DW_0_BASE_ADDR \
|
||||
DT_SNPS_DESIGNWARE_GPIO_80C00_BASE_ADDRESS
|
||||
#define DT_GPIO_DW_0_BITS \
|
||||
DT_SNPS_DESIGNWARE_GPIO_80C00_BITS
|
||||
#define DT_GPIO_DW_0_IRQ \
|
||||
DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0
|
||||
#define CONFIG_GPIO_DW_0_IRQ_PRI \
|
||||
DT_SNPS_DESIGNWARE_GPIO_80C00_IRQ_0_PRIORITY
|
||||
#define DT_GPIO_DW_0_IRQ_FLAGS 0
|
||||
#define CONFIG_GPIO_DW_0_NAME \
|
||||
DT_SNPS_DESIGNWARE_GPIO_80C00_LABEL
|
||||
#define DT_INST_0_SNPS_DESIGNWARE_GPIO_IRQ_0_FLAGS 0
|
||||
|
||||
#define DT_PINMUX_BASE_ADDR \
|
||||
DT_INTEL_S1000_PINMUX_81C30_BASE_ADDRESS
|
||||
|
|
|
@ -36,7 +36,7 @@
|
|||
#define GPIO_OUT_PIN 23
|
||||
#define GPIO_INT_PIN 24
|
||||
#define GPIO_NAME "GPIO_"
|
||||
#define GPIO_DRV_NAME CONFIG_GPIO_DW_0_NAME
|
||||
#define GPIO_DRV_NAME DT_INST_0_SNPS_DESIGNWARE_GPIO_LABEL
|
||||
|
||||
/* size of stack area used by each thread */
|
||||
#define STACKSIZE 1024
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue