aarch64: Rework {inc,dec}_nest_counter
There are several issues with the current implemenation of the {inc,dec}_nest_counter macros. The first problem is that it's internally using a call to a misplaced function called z_arm64_curr_cpu() (for some unknown reason hosted in irq_manage.c) that could potentially clobber the caller-saved registers without any notice to the user of the macro. The second problem is that being a macro the clobbered registers should be specified at the calling site, this is not possible given the current implementation. To fix these issues and make the call quicker, this patch rewrites the code in assembly leveraging the availability of the _curr_cpu array. It now clobbers only two registers passed from the calling site. Signed-off-by: Carlo Caione <ccaione@baylibre.com>
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6a81a99724
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4 changed files with 47 additions and 21 deletions
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@ -70,8 +70,3 @@ void z_irq_spurious(const void *unused)
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z_arm64_fatal_error(K_ERR_SPURIOUS_IRQ, NULL);
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}
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_cpu_t *z_arm64_curr_cpu(void)
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{
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return arch_curr_cpu();
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}
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@ -33,7 +33,7 @@ GTEXT(_isr_wrapper)
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SECTION_FUNC(TEXT, _isr_wrapper)
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/* ++(_kernel->nested) to be checked by arch_is_in_isr() */
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inc_nest_counter
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inc_nest_counter x0, x1
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#ifdef CONFIG_TRACING
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bl sys_trace_isr_enter
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@ -80,7 +80,7 @@ spurious_continue:
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#endif
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/* if (--(_kernel->nested) != 0) exit */
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dec_nest_counter
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dec_nest_counter x0, x1
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bne exit
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@ -9,31 +9,64 @@
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#ifdef _ASMLANGUAGE
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GDATA(_curr_cpu)
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GDATA(_kernel)
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/*
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* Get CPU id
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*/
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.macro z_arm64_get_cpu_id xreg0
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mrs \xreg0, mpidr_el1
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/* FIMXME: aff3 not taken into consideration */
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ubfx \xreg0, \xreg0, #0, #24
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.endm
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/*
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* Get CPU pointer
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*/
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.macro get_cpu xreg0, xreg1
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ldr \xreg0, =_curr_cpu
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z_arm64_get_cpu_id \xreg1
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add \xreg0, \xreg0, \xreg1, lsl #3
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ldr \xreg0, [\xreg0]
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.endm
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/*
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* Increment nested counter
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*/
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.macro inc_nest_counter
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bl z_arm64_curr_cpu
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ldr x1, [x0, #___cpu_t_nested_OFFSET]
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add x1, x1, #1
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str x1, [x0, #___cpu_t_nested_OFFSET]
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.macro inc_nest_counter xreg0, xreg1
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#ifdef CONFIG_SMP
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get_cpu \xreg0, \xreg1
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ldr \xreg1, [\xreg0, #___cpu_t_nested_OFFSET]
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add \xreg1, \xreg1, #1
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str \xreg1, [\xreg0, #___cpu_t_nested_OFFSET]
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#else
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ldr \xreg0, =_kernel
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ldr \xreg1, [\xreg0, #_kernel_offset_to_nested]
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add \xreg1, \xreg1, #1
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str \xreg1, [\xreg0, #_kernel_offset_to_nested]
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#endif
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.endm
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/*
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* Decrement nested counter and update condition flags
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*/
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.macro dec_nest_counter
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bl z_arm64_curr_cpu
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ldr x1, [x0, #___cpu_t_nested_OFFSET]
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subs x1, x1, #1
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str x1, [x0, #___cpu_t_nested_OFFSET]
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.macro dec_nest_counter xreg0, xreg1
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#ifdef CONFIG_SMP
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get_cpu \xreg0, \xreg1
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ldr \xreg1, [\xreg0, #___cpu_t_nested_OFFSET]
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subs \xreg1, \xreg1, #1
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str \xreg1, [\xreg0, #___cpu_t_nested_OFFSET]
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#else
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ldr \xreg0, =_kernel
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ldr \xreg1, [\xreg0, #_kernel_offset_to_nested]
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subs \xreg1, \xreg1, #1
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str \xreg1, [\xreg0, #_kernel_offset_to_nested]
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#endif
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.endm
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#endif /* _ASMLANGUAGE */
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@ -20,8 +20,6 @@
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_ASM_FILE_PROLOGUE
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GDATA(_kernel)
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/*
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* Routine to handle context switches
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*
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@ -119,12 +117,12 @@ SECTION_FUNC(TEXT, z_arm64_sync_exc)
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b inv
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offload:
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/* ++(_kernel->nested) to be checked by arch_is_in_isr() */
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inc_nest_counter
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inc_nest_counter x0, x1
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bl z_irq_do_offload
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/* --(_kernel->nested) */
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dec_nest_counter
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dec_nest_counter x0, x1
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b z_arm64_exit_exc
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#endif
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b inv
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