From bda8ae8c3f067adf5d1c46d5f1ca2bbe42423496 Mon Sep 17 00:00:00 2001 From: Aksel Skauge Mellbye Date: Fri, 20 Sep 2024 16:07:55 +0200 Subject: [PATCH] drivers: clock_control: silabs: Add clock control driver Add clock control driver for Silicon Labs Series 2 and newer. Signed-off-by: Aksel Skauge Mellbye --- .../silabs/dev_kits/sltb010a/sltb010a_0.yaml | 1 + .../dev_kits/xg24_dk2601b/xg24_dk2601b.yaml | 1 + .../dev_kits/xg27_dk2602a/xg27_dk2602a.yaml | 1 + drivers/clock_control/CMakeLists.txt | 1 + drivers/clock_control/Kconfig | 2 + drivers/clock_control/Kconfig.silabs | 9 ++ .../clock_control_silabs_series.c | 127 ++++++++++++++++++ dts/arm/silabs/efr32bg22.dtsi | 12 ++ dts/arm/silabs/efr32bg27.dtsi | 13 ++ dts/arm/silabs/efr32bg2x.dtsi | 8 ++ dts/arm/silabs/efr32mg21.dtsi | 19 +++ dts/arm/silabs/efr32mg24.dtsi | 18 +++ dts/bindings/clock/silabs,series-clock.yaml | 19 +++ .../clock_control/clock_control_silabs.h | 39 ++++++ .../dt-bindings/clock/silabs/common-clock.h | 54 ++++++++ .../dt-bindings/clock/silabs/xg21-clock.h | 26 ++++ .../dt-bindings/clock/silabs/xg22-clock.h | 76 +++++++++++ .../dt-bindings/clock/silabs/xg23-clock.h | 86 ++++++++++++ .../dt-bindings/clock/silabs/xg24-clock.h | 85 ++++++++++++ .../dt-bindings/clock/silabs/xg27-clock.h | 78 +++++++++++ .../src/silabs_device_subsys.h | 31 +++++ .../src/test_clock_control.c | 2 + .../clock_control_api/testcase.yaml | 3 + 23 files changed, 711 insertions(+) create mode 100644 drivers/clock_control/Kconfig.silabs create mode 100644 drivers/clock_control/clock_control_silabs_series.c create mode 100644 dts/bindings/clock/silabs,series-clock.yaml create mode 100644 include/zephyr/drivers/clock_control/clock_control_silabs.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/common-clock.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg21-clock.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg22-clock.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg23-clock.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg24-clock.h create mode 100644 include/zephyr/dt-bindings/clock/silabs/xg27-clock.h create mode 100644 tests/drivers/clock_control/clock_control_api/src/silabs_device_subsys.h diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml index 8cbf1832eac..4de8c502a07 100644 --- a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml +++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml @@ -15,4 +15,5 @@ supported: - uart - i2c - spi + - clock_control vendor: silabs diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml index ed39649abe6..8bfaf749e32 100644 --- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml +++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml @@ -13,6 +13,7 @@ supported: - gpio - uart - watchdog + - clock_control testing: ignore_tags: - pm diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml index bb6a214b786..b725374398e 100644 --- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml +++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml @@ -13,4 +13,5 @@ supported: - counter - gpio - uart + - clock_control vendor: silabs diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt index e08891a42c7..79079867e5d 100644 --- a/drivers/clock_control/CMakeLists.txt +++ b/drivers/clock_control/CMakeLists.txt @@ -25,6 +25,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clo zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC clock_control_rv32m1_pcc.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1 clock_control_ifx_cat1.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM clock_control_sam_pmc.c) +zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SERIES clock_control_silabs_series.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_PLL clock_control_si32_pll.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB clock_control_si32_ahb.c) zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_APB clock_control_si32_apb.c) diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig index 42a5f23ad1f..ca4db637014 100644 --- a/drivers/clock_control/Kconfig +++ b/drivers/clock_control/Kconfig @@ -98,4 +98,6 @@ source "drivers/clock_control/Kconfig.nrf_auxpll" source "drivers/clock_control/Kconfig.arm_scmi" +source "drivers/clock_control/Kconfig.silabs" + endif # CLOCK_CONTROL diff --git a/drivers/clock_control/Kconfig.silabs b/drivers/clock_control/Kconfig.silabs new file mode 100644 index 00000000000..83926fe465c --- /dev/null +++ b/drivers/clock_control/Kconfig.silabs @@ -0,0 +1,9 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +config CLOCK_CONTROL_SILABS_SERIES + bool "Silicon Labs Series 2+ clock control driver" + default y + depends on DT_HAS_SILABS_SERIES_CLOCK_ENABLED + help + Enable Silicon Labs Series 2+ Clock Management Unit clock control driver. diff --git a/drivers/clock_control/clock_control_silabs_series.c b/drivers/clock_control/clock_control_silabs_series.c new file mode 100644 index 00000000000..90498c246e0 --- /dev/null +++ b/drivers/clock_control/clock_control_silabs_series.c @@ -0,0 +1,127 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT silabs_series_clock + +#include +#include +#include +#include + +#include "sl_clock_manager.h" +#include "sl_status.h" + +struct silabs_clock_control_config { + CMU_TypeDef *cmu; +}; + +static enum clock_control_status silabs_clock_control_get_status(const struct device *dev, + clock_control_subsys_t sys); + +static int silabs_clock_control_on(const struct device *dev, clock_control_subsys_t sys) +{ + const struct silabs_clock_control_cmu_config *cfg = sys; + sl_status_t status; + + if (silabs_clock_control_get_status(dev, sys) == CLOCK_CONTROL_STATUS_ON) { + return -EALREADY; + } + + status = sl_clock_manager_enable_bus_clock(&cfg->bus_clock); + if (status != SL_STATUS_OK) { + return -ENOTSUP; + } + + return 0; +} + +static int silabs_clock_control_off(const struct device *dev, clock_control_subsys_t sys) +{ + const struct silabs_clock_control_cmu_config *cfg = sys; + sl_status_t status; + + status = sl_clock_manager_disable_bus_clock(&cfg->bus_clock); + if (status != SL_STATUS_OK) { + return -ENOTSUP; + } + + return 0; +} + +static int silabs_clock_control_get_rate(const struct device *dev, clock_control_subsys_t sys, + uint32_t *rate) +{ + const struct silabs_clock_control_cmu_config *cfg = sys; + sl_status_t status; + + status = sl_clock_manager_get_clock_branch_frequency(cfg->branch, rate); + if (status != SL_STATUS_OK) { + return -ENOTSUP; + } + + return 0; +} + +static enum clock_control_status silabs_clock_control_get_status(const struct device *dev, + clock_control_subsys_t sys) +{ + const struct silabs_clock_control_cmu_config *cfg = sys; + __maybe_unused const struct silabs_clock_control_config *reg = dev->config; + uint32_t clock_status = 0; + + if (cfg->bus_clock == 0xFFFFFFFFUL) { + return CLOCK_CONTROL_STATUS_UNKNOWN; + } + + switch (FIELD_GET(CLOCK_REG_MASK, cfg->bus_clock)) { +#if defined(_CMU_CLKEN0_MASK) + case 0: + clock_status = reg->cmu->CLKEN0; + break; +#endif +#if defined(_CMU_CLKEN1_MASK) + case 1: + clock_status = reg->cmu->CLKEN1; + break; +#endif +#if defined(_CMU_CLKEN2_MASK) + case 2: + clock_status = reg->cmu->CLKEN2; + break; +#endif + default: + __ASSERT(false, "Invalid bus clock: %x\n", cfg->bus_clock); + break; + } + + if (clock_status & BIT(FIELD_GET(CLOCK_BIT_MASK, cfg->bus_clock))) { + return CLOCK_CONTROL_STATUS_ON; + } else { + return CLOCK_CONTROL_STATUS_OFF; + } +} + +static int silabs_clock_control_init(const struct device *dev) +{ + ARG_UNUSED(dev); + sl_clock_manager_runtime_init(); + + return 0; +} + +static const struct clock_control_driver_api silabs_clock_control_api = { + .on = silabs_clock_control_on, + .off = silabs_clock_control_off, + .get_rate = silabs_clock_control_get_rate, + .get_status = silabs_clock_control_get_status, +}; + +static const struct silabs_clock_control_config silabs_clock_control_config = { + .cmu = (CMU_TypeDef *)DT_INST_REG_ADDR(0), +}; + +DEVICE_DT_INST_DEFINE(0, silabs_clock_control_init, NULL, NULL, &silabs_clock_control_config, + PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &silabs_clock_control_api); diff --git a/dts/arm/silabs/efr32bg22.dtsi b/dts/arm/silabs/efr32bg22.dtsi index 1b60f2d7b96..bcf918a9164 100644 --- a/dts/arm/silabs/efr32bg22.dtsi +++ b/dts/arm/silabs/efr32bg22.dtsi @@ -5,8 +5,13 @@ */ #include "efr32bg2x.dtsi" +#include #include +&cmu { + interrupts = <46 0>; +}; + &msc { flash0: flash@0 { compatible = "soc-nv-flash"; @@ -22,28 +27,35 @@ &gpio { interrupts = <10 2 18 2>; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; }; &i2c0 { interrupts = <27 0>; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; }; &i2c1 { interrupts = <28 0>; + clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; }; &usart0 { interrupts = <13 0>, <14 0>; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; }; &usart1 { interrupts = <15 0>, <16 0>; + clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>; }; &burtc0 { interrupts = <18 0>; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; }; &stimer0 { interrupts = <12 0>; + clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>; }; diff --git a/dts/arm/silabs/efr32bg27.dtsi b/dts/arm/silabs/efr32bg27.dtsi index 85ab2bd0db1..448761f3a50 100644 --- a/dts/arm/silabs/efr32bg27.dtsi +++ b/dts/arm/silabs/efr32bg27.dtsi @@ -5,8 +5,13 @@ */ #include "efr32bg2x.dtsi" +#include #include +&cmu { + interrupts = <52 0>; +}; + &msc { flash0: flash@8000000 { compatible = "soc-nv-flash"; @@ -22,32 +27,40 @@ &gpio { interrupts = <30 2 31 2>; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; }; &i2c0 { interrupts = <32 0>; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; }; &i2c1 { interrupts = <33 0>; + clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>; }; &usart0 { interrupts = <16 0>, <17 0>; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; }; &usart1 { interrupts = <18 0>, <19 0>; + clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>; }; &burtc0 { interrupts = <23 0>; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; }; &stimer0 { interrupts = <15 0>; + clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>; }; &adc0 { interrupts = <54 0>; + clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; }; diff --git a/dts/arm/silabs/efr32bg2x.dtsi b/dts/arm/silabs/efr32bg2x.dtsi index 9cd0618cd41..ca42d7c0888 100644 --- a/dts/arm/silabs/efr32bg2x.dtsi +++ b/dts/arm/silabs/efr32bg2x.dtsi @@ -93,6 +93,14 @@ }; soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + interrupt-names = "cmu"; + status = "okay"; + #clock-cells = <2>; + }; + msc: flash-controller@50030000 { compatible = "silabs,gecko-flash-controller"; reg = <0x50030000 0xC69>; diff --git a/dts/arm/silabs/efr32mg21.dtsi b/dts/arm/silabs/efr32mg21.dtsi index 217830f7265..fa6a47f6d8d 100644 --- a/dts/arm/silabs/efr32mg21.dtsi +++ b/dts/arm/silabs/efr32mg21.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include "gpio_gecko.h" / { @@ -40,6 +41,15 @@ }; soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + interrupts = <48 0>; + interrupt-names = "cmu"; + status = "okay"; + #clock-cells = <2>; + }; + msc: flash-controller@50030000 { compatible = "silabs,gecko-flash-controller"; reg = <0x50030000 0x31a4>; @@ -61,6 +71,7 @@ interrupts = <11 0>, <12 0>; interrupt-names = "rx", "tx"; peripheral-id = <0>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>; status = "disabled"; }; @@ -70,6 +81,7 @@ interrupts = <13 0>, <14 0>; interrupt-names = "rx", "tx"; peripheral-id = <1>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>; status = "disabled"; }; @@ -79,6 +91,7 @@ interrupts = <15 0>, <16 0>; interrupt-names = "rx", "tx"; peripheral-id = <2>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>; status = "disabled"; }; @@ -89,6 +102,7 @@ #size-cells = <0>; reg = <0x5a010000 0x400>; interrupts = <27 0>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_LSPCLK>; status = "disabled"; }; @@ -99,6 +113,7 @@ #size-cells = <0>; reg = <0x50068000 0x400>; interrupts = <28 0>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>; status = "disabled"; }; @@ -108,6 +123,7 @@ interrupts = <10 0>; clock-frequency = <32768>; prescaler = <1>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_RTCCCLK>; status = "disabled"; }; @@ -116,6 +132,7 @@ reg = <0x5003c300 0x3c00>; interrupts = <26 2>, <25 2>; interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>; ranges; #address-cells = <1>; @@ -171,6 +188,7 @@ reg = <0x5a018000 0x2C>; peripheral-id = <0>; interrupts = <43 0>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG0CLK>; status = "disabled"; }; @@ -179,6 +197,7 @@ reg = <0x5a01c000 0x2C>; peripheral-id = <1>; interrupts = <44 0>; + clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG1CLK>; status = "disabled"; }; diff --git a/dts/arm/silabs/efr32mg24.dtsi b/dts/arm/silabs/efr32mg24.dtsi index b92100c85a5..540b9b83eac 100644 --- a/dts/arm/silabs/efr32mg24.dtsi +++ b/dts/arm/silabs/efr32mg24.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include / { @@ -84,6 +85,15 @@ }; soc { + cmu: clock@50008000 { + compatible = "silabs,series-clock"; + reg = <0x50008000 0x4000>; + interrupts = <47 0>; + interrupt-names = "cmu"; + status = "okay"; + #clock-cells = <2>; + }; + msc: flash-controller@50030000 { compatible = "silabs,gecko-flash-controller"; reg = <0x50030000 0x3148>; @@ -105,6 +115,7 @@ interrupts = <9 0>, <10 0>; interrupt-names = "rx", "tx"; peripheral-id = <0>; + clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>; status = "disabled"; }; @@ -112,6 +123,7 @@ compatible = "silabs,gecko-burtc"; reg = <0x50064000 0x3034>; interrupts = <17 0>; + clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>; status = "disabled"; }; @@ -130,6 +142,7 @@ #size-cells = <0>; reg = <0x5b000000 0x3044>; interrupts = <27 0>; + clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>; status = "disabled"; }; @@ -139,6 +152,7 @@ interrupts = <67 0>; clock-frequency = <32768>; prescaler = <1>; + clocks = <&cmu CLOCK_SYSRTC0 CLOCK_BRANCH_SYSRTCCLK>; status = "disabled"; }; @@ -147,6 +161,7 @@ reg = <0x5003c000 0x4000>; interrupts = <26 2>, <25 2>; interrupt-names = "GPIO_EVEN", "GPIO_ODD"; + clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>; ranges; #address-cells = <1>; @@ -194,6 +209,7 @@ reg = <0x5b004000 0x2C>; peripheral-id = <0>; interrupts = <42 0>; + clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>; status = "disabled"; }; @@ -202,6 +218,7 @@ reg = <0x5b008000 0x2C>; peripheral-id = <1>; interrupts = <43 0>; + clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>; status = "disabled"; }; @@ -209,6 +226,7 @@ compatible = "silabs,gecko-iadc"; reg = <0x59004000 0x4000>; interrupts = <49 0>; + clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>; status = "disabled"; #io-channel-cells = <1>; }; diff --git a/dts/bindings/clock/silabs,series-clock.yaml b/dts/bindings/clock/silabs,series-clock.yaml new file mode 100644 index 00000000000..de013327390 --- /dev/null +++ b/dts/bindings/clock/silabs,series-clock.yaml @@ -0,0 +1,19 @@ +# Copyright (c) 2024 Silicon Laboratories Inc. +# SPDX-License-Identifier: Apache-2.0 + +description: Silicon Labs Series 2+ clock control node + +compatible: "silabs,series-clock" + +include: [clock-controller.yaml, base.yaml] + +properties: + reg: + required: true + + "#clock-cells": + const: 2 + +clock-cells: + - enable + - branch diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h new file mode 100644 index 00000000000..d608b1da5b0 --- /dev/null +++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ +#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ + +#include + +#if defined(CONFIG_SOC_SERIES_EFR32MG21) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32BG22) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32MG24) +#include +#elif defined(CONFIG_SOC_SERIES_EFR32BG27) +#include +#endif + +struct silabs_clock_control_cmu_config { + uint32_t bus_clock; + uint8_t branch; +}; + +#define SILABS_DT_CLOCK_CFG(node_id) \ + { \ + .bus_clock = DT_CLOCKS_CELL(node_id, enable), \ + .branch = DT_CLOCKS_CELL(node_id, branch), \ + } + +#define SILABS_DT_INST_CLOCK_CFG(inst) \ + { \ + .bus_clock = DT_INST_CLOCKS_CELL(inst, enable), \ + .branch = DT_INST_CLOCKS_CELL(inst, branch), \ + } + +#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_SILABS_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/common-clock.h b/include/zephyr/dt-bindings/clock/silabs/common-clock.h new file mode 100644 index 00000000000..1b5aa5d7a63 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/common-clock.h @@ -0,0 +1,54 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ + +/* + * DT macros for clock branches. + * Must stay in sync with the enum sl_clock_branch_t in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_BRANCH_SYSCLK 0 +#define CLOCK_BRANCH_HCLK 1 +#define CLOCK_BRANCH_HCLKRADIO 2 +#define CLOCK_BRANCH_PCLK 3 +#define CLOCK_BRANCH_LSPCLK 4 +#define CLOCK_BRANCH_TRACECLK 5 +#define CLOCK_BRANCH_ADCCLK 6 +#define CLOCK_BRANCH_EXPORTCLK 7 +#define CLOCK_BRANCH_EM01GRPACLK 8 +#define CLOCK_BRANCH_EM01GRPBCLK 9 +#define CLOCK_BRANCH_EM01GRPCCLK 10 +#define CLOCK_BRANCH_EM01GRPDCLK 11 +#define CLOCK_BRANCH_EM23GRPACLK 12 +#define CLOCK_BRANCH_EM4GRPACLK 13 +#define CLOCK_BRANCH_QSPISYSCLK 14 +#define CLOCK_BRANCH_IADCCLK 15 +#define CLOCK_BRANCH_WDOG0CLK 16 +#define CLOCK_BRANCH_WDOG1CLK 17 +#define CLOCK_BRANCH_RTCCCLK 18 +#define CLOCK_BRANCH_SYSRTCCLK 19 +#define CLOCK_BRANCH_EUART0CLK 20 +#define CLOCK_BRANCH_EUSART0CLK 21 +#define CLOCK_BRANCH_DPLLREFCLK 22 +#define CLOCK_BRANCH_I2C0CLK 23 +#define CLOCK_BRANCH_LCDCLK 24 +#define CLOCK_BRANCH_PIXELRZCLK 25 +#define CLOCK_BRANCH_PCNT0CLK 26 +#define CLOCK_BRANCH_PRORTCCLK 27 +#define CLOCK_BRANCH_SYSTICKCLK 28 +#define CLOCK_BRANCH_LESENSEHFCLK 29 +#define CLOCK_BRANCH_VDAC0CLK 30 +#define CLOCK_BRANCH_VDAC1CLK 31 +#define CLOCK_BRANCH_USB0CLK 32 +#define CLOCK_BRANCH_FLPLLREFCLK 33 +#define CLOCK_BRANCH_INVALID 34 + +#define CLOCK_BIT_MASK 0x03FUL +#define CLOCK_REG_MASK 0x1C0UL + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_COMMON_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h new file mode 100644 index 00000000000..dcfcb4aeb84 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg21-clock.h @@ -0,0 +1,26 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_AUTO 0xFFFFFFFFUL + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG21_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h new file mode 100644 index 00000000000..ef9c8623b53 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg22-clock.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_EUART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG22_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h new file mode 100644 index 00000000000..29914ecdf23 --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg23-clock.h @@ -0,0 +1,86 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_EUSART2 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LCD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LESENSE (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG23_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h new file mode 100644 index 00000000000..7fca2a5baaf --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg24-clock.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ACMP1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DMEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ECAIFADC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_EUSART1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFRCOEM23 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_HOSTMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_KEYSCAN (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_MVP (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_PCNT0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFECA0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_RFECA1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_RFMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RFSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_SEMAILBOX (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_SYSRTC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 24)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_VDAC0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_VDAC1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_WDOG1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG24_CLOCK_H_ */ diff --git a/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h new file mode 100644 index 00000000000..c21a9e5cc9c --- /dev/null +++ b/include/zephyr/dt-bindings/clock/silabs/xg27-clock.h @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * This file was generated by the script gen_clock_control.py in the hal_silabs module. + * Do not manually edit. + */ + +#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ +#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ + +#include +#include "common-clock.h" + +/* + * DT macros for clock tree nodes. + * Defined as: + * 0..5 - Bit within CLKEN register + * 6..8 - CLKEN register number + * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be + * interpreted correctly by the clock control driver. + */ +#define CLOCK_ACMP0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_AGC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_AMUXCP0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BUFC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11)) +#define CLOCK_BURAM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_BURTC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29)) +#define CLOCK_CRYPTOACC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 13)) +#define CLOCK_DCDC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31)) +#define CLOCK_DPLL0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_ETAMPDET (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28)) +#define CLOCK_EUSART0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_FRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_FSRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20)) +#define CLOCK_GPCRC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3)) +#define CLOCK_GPIO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26)) +#define CLOCK_HFRCO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_HFXO0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19)) +#define CLOCK_I2C0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_I2C1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_IADC0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_ICACHE0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_IFADCDEBUG (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LDMA0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0)) +#define CLOCK_LDMAXBAR0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_LETIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12)) +#define CLOCK_LFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21)) +#define CLOCK_LFXO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22)) +#define CLOCK_MODEM (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1)) +#define CLOCK_MSC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17)) +#define CLOCK_PDM (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25)) +#define CLOCK_PRORTC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10)) +#define CLOCK_PROTIMER (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_PRS (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27)) +#define CLOCK_RAC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_RADIOAES (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RDMAILBOX0 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_RDMAILBOX1 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_RDSCRATCHPAD (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_RFCRC (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2)) +#define CLOCK_RFSENSE (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14)) +#define CLOCK_RTCC (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30)) +#define CLOCK_SMU (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15)) +#define CLOCK_SYNTH (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_SYSCFG (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16)) +#define CLOCK_TIMER0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4)) +#define CLOCK_TIMER1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5)) +#define CLOCK_TIMER2 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6)) +#define CLOCK_TIMER3 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7)) +#define CLOCK_TIMER4 (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18)) +#define CLOCK_ULFRCO (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23)) +#define CLOCK_USART0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8)) +#define CLOCK_USART1 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9)) +#define CLOCK_WDOG0 (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13)) + +#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG27_CLOCK_H_ */ diff --git a/tests/drivers/clock_control/clock_control_api/src/silabs_device_subsys.h b/tests/drivers/clock_control/clock_control_api/src/silabs_device_subsys.h new file mode 100644 index 00000000000..e3362303ac8 --- /dev/null +++ b/tests/drivers/clock_control/clock_control_api/src/silabs_device_subsys.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2024 Silicon Laboratories Inc. + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "device_subsys.h" +#include + +struct silabs_clock_control_cmu_config i2c0_clock = { + .bus_clock = CLOCK_I2C0, + .branch = CLOCK_BRANCH_LSPCLK, +}; + +struct silabs_clock_control_cmu_config wdog0_clock = { + .bus_clock = CLOCK_WDOG0, + .branch = CLOCK_BRANCH_WDOG0CLK, +}; + +static const struct device_subsys_data subsys_data[] = { + {.subsys = (void *)&i2c0_clock}, + {.subsys = (void *)&wdog0_clock}, +}; + +static const struct device_data devices[] = { + { + .dev = DEVICE_DT_GET_ONE(silabs_series_clock), + .subsys_data = subsys_data, + .subsys_cnt = ARRAY_SIZE(subsys_data) + } +}; diff --git a/tests/drivers/clock_control/clock_control_api/src/test_clock_control.c b/tests/drivers/clock_control/clock_control_api/src/test_clock_control.c index 80a62132702..2c857d28270 100644 --- a/tests/drivers/clock_control/clock_control_api/src/test_clock_control.c +++ b/tests/drivers/clock_control/clock_control_api/src/test_clock_control.c @@ -12,6 +12,8 @@ LOG_MODULE_REGISTER(test); #include "nrf_device_subsys.h" #elif DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_rtc) #include "esp32_device_subsys.h" +#elif DT_HAS_COMPAT_STATUS_OKAY(silabs_series_clock) +#include "silabs_device_subsys.h" #else #error "Unsupported board" #endif diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml index ece53e013d7..19644639cd8 100644 --- a/tests/drivers/clock_control/clock_control_api/testcase.yaml +++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml @@ -10,6 +10,9 @@ tests: - esp32c3_devkitm - esp32s2_saola - esp32s3_devkitm/esp32s3/procpu + - sltb010a@0 + - xg24_dk2601b + - xg27_dk2602a drivers.clock.clock_control_nrf5: platform_allow: - nrf51dk/nrf51822