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arm64: implement CONFIG_IRQ_OFFLOAD_NESTED

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It can easily be done now, so why not. Suffice to increment the nested
count like with actual IRQs.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2022-03-11 21:29:06 -05:00 • committed by Anas Nashif
commit bd941bcc68
2 changed files with 10 additions and 6 deletions
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1
arch/Kconfig
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@ -46,6 +46,7 @@ config ARM64
select ARCH_HAS_THREAD_LOCAL_STORAGE select ARCH_HAS_THREAD_LOCAL_STORAGE
select USE_SWITCH select USE_SWITCH
select USE_SWITCH_SUPPORTED select USE_SWITCH_SUPPORTED
select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD
help help
ARM64 (AArch64) architecture ARM64 (AArch64) architecture

15
arch/arm64/core/switch.S
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@ -154,16 +154,19 @@ offload:
*/ */
ldp x1, x0, [sp, ___esf_t_x0_x1_OFFSET] ldp x1, x0, [sp, ___esf_t_x0_x1_OFFSET]
/* _current_cpu->nested=1, to be checked by arch_is_in_isr() */ /* ++_current_cpu->nested to be checked by arch_is_in_isr() */
get_cpu x2 get_cpu x2
mov w3, #1 ldr w3, [x2, #___cpu_t_nested_OFFSET]
str w3, [x2, #___cpu_t_nested_OFFSET] add w4, w3, #1
/* switch to IRQ stack and save current sp on it. */ str w4, [x2, #___cpu_t_nested_OFFSET]
/* If not nested: switch to IRQ stack and save current sp on it. */
cbnz w3, 1f
ldr x3, [x2, #___cpu_t_irq_stack_OFFSET] ldr x3, [x2, #___cpu_t_irq_stack_OFFSET]
mov x4, sp mov x4, sp
mov sp, x3 mov sp, x3
str x4, [sp, #-16]! str x4, [sp, #-16]!
1:
/* Execute provided routine (argument is in x0 already). */ /* Execute provided routine (argument is in x0 already). */
blr x1 blr x1