From bd892bd9632fa5eb9c96b0d55666a436ec9a02ce Mon Sep 17 00:00:00 2001 From: Michal Sieron Date: Mon, 11 Apr 2022 16:29:24 +0200 Subject: [PATCH] ethernet: eth_liteeth: Add and use register names Adds addresses and names for individual CSR registers to device tree. This way liteuart driver no longer depends on CSR data width being 8 bits. Also when register names or their number changes, then overlay generated by LiteX will be incompatible with one defined here. This should make finding breaking changes easier. I also appended `_ADDR` suffix to defines, to distinguish them from normal values like `LITEETH_EV_RX`. Signed-off-by: Michal Sieron --- drivers/ethernet/eth_liteeth.c | 68 +++++++++++++-------------- dts/riscv/riscv32-litex-vexriscv.dtsi | 23 ++++++++- 2 files changed, 54 insertions(+), 37 deletions(-) diff --git a/drivers/ethernet/eth_liteeth.c b/drivers/ethernet/eth_liteeth.c index 13277cb95bc..7708a75e826 100644 --- a/drivers/ethernet/eth_liteeth.c +++ b/drivers/ethernet/eth_liteeth.c @@ -29,30 +29,28 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME); #define LITEETH_EV_RX 0x1 /* slots */ -#define LITEETH_SLOT_BASE DT_INST_REG_ADDR_BY_NAME(0, buffers) -#define LITEETH_SLOT_RX0 ((LITEETH_SLOT_BASE) + 0x0000) -#define LITEETH_SLOT_RX1 ((LITEETH_SLOT_BASE) + 0x0800) -#define LITEETH_SLOT_TX0 ((LITEETH_SLOT_BASE) + 0x1000) -#define LITEETH_SLOT_TX1 ((LITEETH_SLOT_BASE) + 0x1800) +#define LITEETH_SLOT_BASE_ADDR DT_INST_REG_ADDR_BY_NAME(0, buffers) +#define LITEETH_SLOT_RX0_ADDR (LITEETH_SLOT_BASE_ADDR + 0x0000) +#define LITEETH_SLOT_RX1_ADDR (LITEETH_SLOT_BASE_ADDR + 0x0800) +#define LITEETH_SLOT_TX0_ADDR (LITEETH_SLOT_BASE_ADDR + 0x1000) +#define LITEETH_SLOT_TX1_ADDR (LITEETH_SLOT_BASE_ADDR + 0x1800) /* sram - rx */ -#define LITEETH_RX_BASE DT_INST_REG_ADDR_BY_NAME(0, control) -#define LITEETH_RX_SLOT ((LITEETH_RX_BASE) + 0x00) -#define LITEETH_RX_LENGTH ((LITEETH_RX_BASE) + 0x04) -#define LITEETH_RX_EV_PENDING ((LITEETH_RX_BASE) + 0x28) -#define LITEETH_RX_EV_ENABLE ((LITEETH_RX_BASE) + 0x2c) +#define LITEETH_RX_SLOT_ADDR DT_INST_REG_ADDR_BY_NAME(0, rx_slot) +#define LITEETH_RX_LENGTH_ADDR DT_INST_REG_ADDR_BY_NAME(0, rx_length) +#define LITEETH_RX_EV_PENDING_ADDR DT_INST_REG_ADDR_BY_NAME(0, rx_ev_pending) +#define LITEETH_RX_EV_ENABLE_ADDR DT_INST_REG_ADDR_BY_NAME(0, rx_ev_enable) /* sram - tx */ -#define LITEETH_TX_BASE ((DT_INST_REG_ADDR_BY_NAME(0, control)) + 0x30) -#define LITEETH_TX_START ((LITEETH_TX_BASE) + 0x00) -#define LITEETH_TX_READY ((LITEETH_TX_BASE) + 0x04) -#define LITEETH_TX_SLOT ((LITEETH_TX_BASE) + 0x0c) -#define LITEETH_TX_LENGTH ((LITEETH_TX_BASE) + 0x10) -#define LITEETH_TX_EV_PENDING ((LITEETH_TX_BASE) + 0x1c) +#define LITEETH_TX_START_ADDR DT_INST_REG_ADDR_BY_NAME(0, tx_start) +#define LITEETH_TX_READY_ADDR DT_INST_REG_ADDR_BY_NAME(0, tx_ready) +#define LITEETH_TX_SLOT_ADDR DT_INST_REG_ADDR_BY_NAME(0, tx_slot) +#define LITEETH_TX_LENGTH_ADDR DT_INST_REG_ADDR_BY_NAME(0, tx_length) +#define LITEETH_TX_EV_PENDING_ADDR DT_INST_REG_ADDR_BY_NAME(0, tx_ev_pending) /* irq */ -#define LITEETH_IRQ DT_INST_IRQN(0) -#define LITEETH_IRQ_PRIORITY DT_INST_IRQ(0, priority) +#define LITEETH_IRQ DT_INST_IRQN(0) +#define LITEETH_IRQ_PRIORITY DT_INST_IRQ(0, priority) #define MAX_TX_FAILURE 100 @@ -93,11 +91,11 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) len = net_pkt_get_len(pkt); net_pkt_read(pkt, context->tx_buf[context->txslot], len); - litex_write8(context->txslot, LITEETH_TX_SLOT); - litex_write16(len, LITEETH_TX_LENGTH); + litex_write8(context->txslot, LITEETH_TX_SLOT_ADDR); + litex_write16(len, LITEETH_TX_LENGTH_ADDR); /* wait for the device to be ready to transmit */ - while (litex_read8(LITEETH_TX_READY) == 0) { + while (litex_read8(LITEETH_TX_READY_ADDR) == 0) { if (attempts++ == MAX_TX_FAILURE) { goto error; } @@ -105,7 +103,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt) } /* start transmitting */ - litex_write8(1, LITEETH_TX_START); + litex_write8(1, LITEETH_TX_START_ADDR); /* change slot */ context->txslot = (context->txslot + 1) % 2; @@ -131,10 +129,10 @@ static void eth_rx(const struct device *port) key = irq_lock(); /* get frame's length */ - len = litex_read32(LITEETH_RX_LENGTH); + len = litex_read32(LITEETH_RX_LENGTH_ADDR); /* which slot is the frame in */ - context->rxslot = litex_read8(LITEETH_RX_SLOT); + context->rxslot = litex_read8(LITEETH_RX_SLOT_ADDR); /* obtain rx buffer */ pkt = net_pkt_rx_alloc_with_buffer(context->iface, len, AF_UNSPEC, 0, @@ -165,19 +163,19 @@ out: static void eth_irq_handler(const struct device *port) { /* check sram reader events (tx) */ - if (litex_read8(LITEETH_TX_EV_PENDING) & LITEETH_EV_TX) { + if (litex_read8(LITEETH_TX_EV_PENDING_ADDR) & LITEETH_EV_TX) { /* TX event is not enabled nor used by this driver; ack just * in case if some rogue TX event appeared */ - litex_write8(LITEETH_EV_TX, LITEETH_TX_EV_PENDING); + litex_write8(LITEETH_EV_TX, LITEETH_TX_EV_PENDING_ADDR); } /* check sram writer events (rx) */ - if (litex_read8(LITEETH_RX_EV_PENDING) & LITEETH_EV_RX) { + if (litex_read8(LITEETH_RX_EV_PENDING_ADDR) & LITEETH_EV_RX) { eth_rx(port); /* ack writer irq */ - litex_write8(LITEETH_EV_RX, LITEETH_RX_EV_PENDING); + litex_write8(LITEETH_EV_RX, LITEETH_RX_EV_PENDING_ADDR); } } @@ -222,18 +220,18 @@ static void eth_iface_init(struct net_if *iface) } /* clear pending events */ - litex_write8(LITEETH_EV_TX, LITEETH_TX_EV_PENDING); - litex_write8(LITEETH_EV_RX, LITEETH_RX_EV_PENDING); + litex_write8(LITEETH_EV_TX, LITEETH_TX_EV_PENDING_ADDR); + litex_write8(LITEETH_EV_RX, LITEETH_RX_EV_PENDING_ADDR); /* setup tx slots */ context->txslot = 0; - context->tx_buf[0] = (uint8_t *)LITEETH_SLOT_TX0; - context->tx_buf[1] = (uint8_t *)LITEETH_SLOT_TX1; + context->tx_buf[0] = (uint8_t *)LITEETH_SLOT_TX0_ADDR; + context->tx_buf[1] = (uint8_t *)LITEETH_SLOT_TX1_ADDR; /* setup rx slots */ context->rxslot = 0; - context->rx_buf[0] = (uint8_t *)LITEETH_SLOT_RX0; - context->rx_buf[1] = (uint8_t *)LITEETH_SLOT_RX1; + context->rx_buf[0] = (uint8_t *)LITEETH_SLOT_RX0_ADDR; + context->rx_buf[1] = (uint8_t *)LITEETH_SLOT_RX1_ADDR; init_done = true; } @@ -260,7 +258,7 @@ static void eth_irq_config(void) IRQ_CONNECT(LITEETH_IRQ, LITEETH_IRQ_PRIORITY, eth_irq_handler, DEVICE_DT_INST_GET(0), 0); irq_enable(LITEETH_IRQ); - litex_write8(1, LITEETH_RX_EV_ENABLE); + litex_write8(1, LITEETH_RX_EV_ENABLE_ADDR); } #endif /* CONFIG_ETH_LITEETH_0 */ diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi index f95d6b9c431..49b583e8c91 100644 --- a/dts/riscv/riscv32-litex-vexriscv.dtsi +++ b/dts/riscv/riscv32-litex-vexriscv.dtsi @@ -104,9 +104,28 @@ compatible = "litex,eth0"; interrupt-parent = <&intc0>; interrupts = <3 0>; - reg = <0xe0009800 0x6b 0xb0000000 0x2000>; + reg = <0xe0009800 0x4 + 0xe0009804 0x8 + 0xe0009828 0x4 + 0xe000982c 0x4 + 0xe0009830 0x4 + 0xe0009834 0x4 + 0xe000983c 0x4 + 0xe0009840 0x8 + 0xe000984c 0x4 + 0xb0000000 0x2000>; local-mac-address = [10 e2 d5 00 00 02]; - reg-names = "control", "buffers"; + reg-names = + "rx_slot", + "rx_length", + "rx_ev_pending", + "rx_ev_enable", + "tx_start", + "tx_ready", + "tx_slot", + "tx_length", + "tx_ev_pending", + "buffers"; label = "eth0"; status = "disabled"; };