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riscv32: enable gen_isr_tables mechanism

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Change-Id: Ia09d9a4d3412424dcbb25db829059a0714d81214
Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2017-02-13 10:11:54 -08:00
commit bd69c3bdf0
7 changed files with 36 additions and 104 deletions
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10
arch/common/Makefile.gen_isr_tables
View file

@ -2,14 +2,10 @@ GEN_ISR_TABLE := $(srctree)/arch/common/gen_isr_tables.py
OUTPUT_SRC := isr_tables.c OUTPUT_SRC := isr_tables.c
OUTPUT_OBJ := isr_tables.o OUTPUT_OBJ := isr_tables.o
ifeq ($(ARCH),arm) ifeq ($(ARCH),riscv32)
OUTPUT_FORMAT := elf32-littlearm OUTPUT_FORMAT := elf32-littleriscv
OUTPUT_ARCH := arm
else ifeq ($(ARCH),nios2)
OUTPUT_FORMAT := elf32-littlenios2
OUTPUT_ARCH := nios2
else else
$(error Output formats not defined for this architecture) OUTPUT_FORMAT := elf32-little$(ARCH)
endif endif
GEN_ISR_TABLE_EXTRA_ARGS := GEN_ISR_TABLE_EXTRA_ARGS :=

7
arch/riscv32/Kconfig
View file

@ -63,6 +63,13 @@ config RISCV_HAS_CPU_IDLE
default n default n
help help
Does SOC has CPU IDLE instruction Does SOC has CPU IDLE instruction
config GEN_ISR_TABLES
default y
config GEN_IRQ_VECTOR_TABLE
default n
endmenu endmenu
source "arch/riscv32/soc/*/Kconfig" source "arch/riscv32/soc/*/Kconfig"

2
arch/riscv32/core/Makefile
View file

@ -1,5 +1,5 @@
ccflags-y += -I$(srctree)/kernel/unified/include ccflags-y += -I$(srctree)/kernel/unified/include
ccflags-y +=-I$(srctree)/arch/$(ARCH)/include ccflags-y +=-I$(srctree)/arch/$(ARCH)/include
obj-y += isr.o reset.o sw_isr_table.o fatal.o irq_manage.o \ obj-y += isr.o reset.o fatal.o irq_manage.o \
prep_c.o cpu_idle.o swap.o thread.o irq_offload.o prep_c.o cpu_idle.o swap.o thread.o irq_offload.o

49
arch/riscv32/core/sw_isr_table.S
View file

@ -1,49 +0,0 @@
/* sw_isr_table.S - ISR table for static ISR declarations for RISCV32 */
/*
* Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <toolchain.h>
#include <sections.h>
#include <arch/cpu.h>
/*
* enable preprocessor features, such
* as %expr - evaluate the expression and use it as a string
*/
.altmacro
/*
* Define an ISR table entry
* Define symbol as weak and give the section .gnu.linkonce
* prefix. This allows linker overload the symbol and the
* whole section by the one defined by a device driver
*/
.macro _isr_table_entry_declare index
WDATA(_isr_irq\index)
.section .gnu.linkonce.isr_irq\index
_isr_irq\index: .word 0xABAD1DEA, _irq_spurious
.endm
/*
* Declare the ISR table
*/
.macro _isr_table_declare from, to
counter = \from
.rept (\to - \from)
_isr_table_entry_declare %counter
counter = counter + 1
.endr
.endm
GTEXT(_irq_spurious)
GDATA(_sw_isr_table)
.section .isr_irq0
.align
_sw_isr_table:
_isr_table_declare 0 CONFIG_NUM_IRQS

21
include/arch/riscv32/arch.h
View file

@ -56,6 +56,7 @@ extern uint32_t __soc_get_irq(void);
void _arch_irq_enable(unsigned int irq); void _arch_irq_enable(unsigned int irq);
void _arch_irq_disable(unsigned int irq); void _arch_irq_disable(unsigned int irq);
int _arch_irq_is_enabled(unsigned int irq); int _arch_irq_is_enabled(unsigned int irq);
void _irq_spurious(void *unused);
/** /**
@ -63,20 +64,6 @@ int _arch_irq_is_enabled(unsigned int irq);
* *
* All arguments must be computable by the compiler at build time. * All arguments must be computable by the compiler at build time.
* *
* Internally this function does a few things:
*
* 1. The enum statement has no effect but forces the compiler to only
* accept constant values for the irq_p parameter, very important as the
* numerical IRQ line is used to create a named section.
*
* 2. An instance of struct _isr_table_entry is created containing the ISR and
* its parameter. If you look at how _sw_isr_table is created, each entry in
* the array is in its own section named by the IRQ line number. What we are
* doing here is to override one of the default entries (which points to the
* spurious IRQ handler) with what was supplied here.
*
* 3. interrupt priority is not supported by pulpino core
*
* @param irq_p IRQ line number * @param irq_p IRQ line number
* @param priority_p Interrupt priority * @param priority_p Interrupt priority
* @param isr_p Interrupt service routine * @param isr_p Interrupt service routine
@ -87,11 +74,7 @@ int _arch_irq_is_enabled(unsigned int irq);
*/ */
#define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \ #define _ARCH_IRQ_CONNECT(irq_p, priority_p, isr_p, isr_param_p, flags_p) \
({ \ ({ \
enum { IRQ = irq_p }; \ _ISR_DECLARE(irq_p, 0, isr_p, isr_param_p); \
static struct _isr_table_entry _CONCAT(_isr_irq, irq_p) \
__attribute__ ((used)) \
__attribute__ ((section(STRINGIFY(_CONCAT(.gnu.linkonce.isr_irq, irq_p))))) = \
{isr_param_p, isr_p}; \
irq_p; \ irq_p; \
}) })

25
include/arch/riscv32/common/linker.ld
View file

@ -37,6 +37,8 @@ MEMORY
{ {
ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE ROM (rx) : ORIGIN = CONFIG_RISCV_ROM_BASE_ADDR, LENGTH = CONFIG_RISCV_ROM_SIZE
RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE RAM (rwx) : ORIGIN = CONFIG_RISCV_RAM_BASE_ADDR, LENGTH = RISCV_RAM_SIZE
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
} }
SECTIONS SECTIONS
@ -69,20 +71,11 @@ SECTIONS
SECTION_PROLOGUE(_TEXT_SECTION_NAME,,) SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
{ {
. = ALIGN(4); . = ALIGN(4);
#ifdef CONFIG_GEN_SW_ISR_TABLE
KEEP(*(.isr_irq*)) KEEP(*(SW_ISR_TABLE))
#endif
/* sections for IRQ0-9 */ KEEP(*(.openocd_debug))
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9]))) KEEP(*(".openocd_debug.*"))
/* sections for IRQ10-99 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
/* sections for IRQ100-999 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
KEEP(*(.openocd_debug))
KEEP(*(".openocd_debug.*"))
_image_text_start = .; _image_text_start = .;
*(.text) *(.text)
@ -160,5 +153,9 @@ SECTIONS
_image_ram_end = .; _image_ram_end = .;
_end = .; /* end of image */ _end = .; /* end of image */
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
GROUP_END(RAMABLE_REGION) GROUP_END(RAMABLE_REGION)
} }

26
include/arch/riscv32/pulpino/linker.ld
View file

@ -33,6 +33,8 @@ MEMORY
{ {
INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE INSTRRAM (wx) : ORIGIN = CONFIG_ITCM_BASE_ADDRESS, LENGTH = CONFIG_ITCM_SIZE
DATARAM (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE DATARAM (rw) : ORIGIN = CONFIG_DTCM_BASE_ADDRESS, LENGTH = CONFIG_DTCM_SIZE
/* Used by and documented in include/linker/intlist.ld */
IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
} }
SECTIONS SECTIONS
@ -80,9 +82,12 @@ SECTIONS
SECTION_PROLOGUE(_RODATA_SECTION_NAME,,) SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
{ {
. = ALIGN(4); . = ALIGN(4);
*(.rodata) #ifdef CONFIG_GEN_SW_ISR_TABLE
*(".rodata.*") KEEP(*(SW_ISR_TABLE))
*(.gnu.linkonce.r.*) #endif
*(.rodata)
*(".rodata.*")
*(.gnu.linkonce.r.*)
} GROUP_LINK_IN(RAMABLE_REGION) } GROUP_LINK_IN(RAMABLE_REGION)
#include <linker/common-ram.ld> #include <linker/common-ram.ld>
@ -91,17 +96,6 @@ SECTIONS
{ {
. = ALIGN(4); . = ALIGN(4);
KEEP(*(.isr_irq*))
/* sections for IRQ0-9 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9])))
/* sections for IRQ10-99 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9])))
/* sections for IRQ100-999 */
KEEP(*(SORT(.gnu.linkonce.isr_irq[0-9][0-9][0-9])))
*(.data) *(.data)
*(".data.*") *(".data.*")
@ -142,5 +136,9 @@ SECTIONS
_end = .; /* end of image */ _end = .; /* end of image */
#ifdef CONFIG_GEN_ISR_TABLES
#include <linker/intlist.ld>
#endif
GROUP_END(RAMABLE_REGION) GROUP_END(RAMABLE_REGION)
} }