drivers: serial: uart_sam0: rework devicetree support
Rework the devicetree to utilize new DT_INST macros and extract per instance data for clocks and dma from devicetree. We update the atmel,sam0-uart binding for dma to replace the rxdma and txdma properties with proper 'dmas' property. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
This commit is contained in:
Kumar Gala
Kumar Gala
parent
70ae3361f8
commit
bd639fc332
2 changed files with 56 additions and 117 deletions
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@ -1045,15 +1045,14 @@ static const struct uart_driver_api uart_sam0_driver_api = {
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};
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};
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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#if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API
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#define DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m) DT_ATMEL_SAM0_UART_SERCOM_ ## n ## _IRQ_ ## m
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#define DT_ATMEL_SAM0_UART_SERCOM_IRQ_PRIORITY(n, m) DT_ATMEL_SAM0_UART_SERCOM_ ## n ## _IRQ_ ## m ## _PRIORITY
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#define SAM0_UART_IRQ_CONNECT(n, m) \
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#define SAM0_UART_IRQ_CONNECT(n, m) \
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do { \
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do { \
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IRQ_CONNECT(DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m), \
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IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq), \
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DT_ATMEL_SAM0_UART_SERCOM_IRQ_PRIORITY(n, m), \
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DT_INST_IRQ_BY_IDX(n, m, priority), \
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uart_sam0_isr, DEVICE_GET(uart_sam0_##n), 0); \
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uart_sam0_isr, \
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irq_enable(DT_ATMEL_SAM0_UART_SERCOM_IRQ(n, m)); \
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DEVICE_GET(uart_sam0_##n), 0); \
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irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq)); \
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} while (0)
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} while (0)
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#define UART_SAM0_IRQ_HANDLER_DECL(n) \
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#define UART_SAM0_IRQ_HANDLER_DECL(n) \
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@ -1084,120 +1083,53 @@ static void uart_sam0_irq_config_##n(struct device *dev) \
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#endif
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#endif
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#if CONFIG_UART_ASYNC_API
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#if CONFIG_UART_ASYNC_API
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA
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#define UART_SAM0_DMA_CHANNELS(n) \
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#define DT_ATMEL_SAM0_UART_SERCOM_0_TXDMA 0xFFU
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.tx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, tx), \
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#endif
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.tx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, tx), \
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA
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.rx_dma_request = ATMEL_SAM0_DT_INST_DMA_TRIGSRC(n, rx), \
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#define DT_ATMEL_SAM0_UART_SERCOM_0_RXDMA 0xFFU
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.rx_dma_channel = ATMEL_SAM0_DT_INST_DMA_CHANNEL(n, rx),
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_1_TXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_1_RXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_2_TXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_2_RXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_3_TXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_3_RXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_4_TXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_4_RXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_5_TXDMA 0xFFU
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#endif
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#ifndef DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA
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#define DT_ATMEL_SAM0_UART_SERCOM_5_RXDMA 0xFFU
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#endif
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#define UART_SAM0_DMA_CHANNELS(n) \
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.tx_dma_request = SERCOM##n##_DMAC_ID_TX, \
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.tx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_TXDMA, \
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.rx_dma_request = SERCOM##n##_DMAC_ID_RX, \
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.rx_dma_channel = DT_ATMEL_SAM0_UART_SERCOM_##n##_RXDMA
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#else
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#else
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#define UART_SAM0_DMA_CHANNELS(n)
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#define UART_SAM0_DMA_CHANNELS(n)
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#endif
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#endif
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#define UART_SAM0_SERCOM_PADS(n) \
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#define UART_SAM0_SERCOM_PADS(n) \
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(DT_ATMEL_SAM0_UART_SERCOM_##n##_RXPO << SERCOM_USART_CTRLA_RXPO_Pos) | \
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(DT_INST_PROP(n, rxpo) << SERCOM_USART_CTRLA_RXPO_Pos) | \
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(DT_ATMEL_SAM0_UART_SERCOM_##n##_TXPO << SERCOM_USART_CTRLA_TXPO_Pos)
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(DT_INST_PROP(n, txpo) << SERCOM_USART_CTRLA_TXPO_Pos)
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#ifdef MCLK
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#ifdef MCLK
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#define UART_SAM0_CONFIG_DEFN(n) \
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#define UART_SAM0_CONFIG_DEFN(n) \
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static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
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static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
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.regs = (SercomUsart *)DT_ATMEL_SAM0_UART_SERCOM_##n##_BASE_ADDRESS, \
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.regs = (SercomUsart *)DT_INST_REG_ADDR(n), \
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.baudrate = DT_ATMEL_SAM0_UART_SERCOM_##n##_CURRENT_SPEED, \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.mclk = MCLK_SERCOM##n, \
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.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
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.mclk_mask = MCLK_SERCOM##n##_MASK, \
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.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
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.gclk_core_id = SERCOM##n##_GCLK_ID_CORE, \
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.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
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.pads = UART_SAM0_SERCOM_PADS(n), \
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.pads = UART_SAM0_SERCOM_PADS(n), \
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UART_SAM0_IRQ_HANDLER_FUNC(n) \
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UART_SAM0_IRQ_HANDLER_FUNC(n) \
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UART_SAM0_DMA_CHANNELS(n) \
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UART_SAM0_DMA_CHANNELS(n) \
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}
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}
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#else
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#else
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#define UART_SAM0_CONFIG_DEFN(n) \
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#define UART_SAM0_CONFIG_DEFN(n) \
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static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
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static const struct uart_sam0_dev_cfg uart_sam0_config_##n = { \
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.regs = (SercomUsart *)DT_ATMEL_SAM0_UART_SERCOM_##n##_BASE_ADDRESS, \
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.regs = (SercomUsart *)DT_INST_REG_ADDR(n), \
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.baudrate = DT_ATMEL_SAM0_UART_SERCOM_##n##_CURRENT_SPEED, \
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.baudrate = DT_INST_PROP(n, current_speed), \
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.pm_apbcmask = PM_APBCMASK_SERCOM##n, \
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.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)), \
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.gclk_clkctrl_id = GCLK_CLKCTRL_ID_SERCOM##n##_CORE, \
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.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
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.pads = UART_SAM0_SERCOM_PADS(n), \
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.pads = UART_SAM0_SERCOM_PADS(n), \
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UART_SAM0_IRQ_HANDLER_FUNC(n) \
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UART_SAM0_IRQ_HANDLER_FUNC(n) \
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UART_SAM0_DMA_CHANNELS(n) \
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UART_SAM0_DMA_CHANNELS(n) \
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}
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}
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#endif
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#endif
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#define UART_SAM0_DEVICE_INIT(n) \
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#define UART_SAM0_DEVICE_INIT(n) \
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static struct uart_sam0_dev_data uart_sam0_data_##n; \
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static struct uart_sam0_dev_data uart_sam0_data_##n; \
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UART_SAM0_IRQ_HANDLER_DECL(n); \
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UART_SAM0_IRQ_HANDLER_DECL(n); \
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UART_SAM0_CONFIG_DEFN(n); \
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UART_SAM0_CONFIG_DEFN(n); \
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DEVICE_AND_API_INIT(uart_sam0_##n, DT_ATMEL_SAM0_UART_SERCOM_##n##_LABEL, \
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DEVICE_AND_API_INIT(uart_sam0_##n, DT_INST_LABEL(n), \
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uart_sam0_init, &uart_sam0_data_##n, \
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uart_sam0_init, &uart_sam0_data_##n, \
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&uart_sam0_config_##n, PRE_KERNEL_1, \
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&uart_sam0_config_##n, PRE_KERNEL_1, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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CONFIG_KERNEL_INIT_PRIORITY_DEVICE, \
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&uart_sam0_driver_api); \
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&uart_sam0_driver_api); \
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UART_SAM0_IRQ_HANDLER(n)
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UART_SAM0_IRQ_HANDLER(n)
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#if DT_ATMEL_SAM0_UART_SERCOM_0_BASE_ADDRESS
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DT_INST_FOREACH(UART_SAM0_DEVICE_INIT)
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UART_SAM0_DEVICE_INIT(0)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_1_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(1)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_2_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(2)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_3_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(3)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_4_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(4)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_5_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(5)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM_6_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(6)
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#endif
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#if DT_ATMEL_SAM0_UART_SERCOM7_BASE_ADDRESS
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UART_SAM0_DEVICE_INIT(7)
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#endif
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@ -27,12 +27,19 @@ properties:
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required: true
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required: true
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description: Transmit Data Pinout
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description: Transmit Data Pinout
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rxdma:
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dmas:
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type: int
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description: |
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required: false
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Optional TX & RX dma specifiers. Each specifier will have a phandle
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description: Receive DMA channel
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reference to the dmac controller, the channel number, and peripheral
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trigger source.
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txdma:
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For example dmas for TX, RX on SERCOM3
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type: int
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dmas = <&dmac 0 0xb>, <&dmac 0 0xa>;
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required: false
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description: Transmit DMA channel
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dma-names:
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description: |
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Required if the dmas property exists. This should be "tx" and "rx"
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to match the dmas property.
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For example
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dma-names = "tx", "rx";
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